cfg: Add interface config for Dangerous Prototypes Bus Blaster

[openocd.git] / tcl / board / at91cap7a-stk-sdram.cfg

diff --git a/tcl/board/at91cap7a-stk-sdram.cfg b/tcl/board/at91cap7a-stk-sdram.cfg
index 6a7e22b278f6ac116368546b79a33f9f9f4c0a3e..95f1d06e2c9c4c9da120f8c18d140ed0bd3a440d 100644 (file)
--- a/tcl/board/at91cap7a-stk-sdram.cfg
+++ b/tcl/board/at91cap7a-stk-sdram.cfg
@@ -15,7 +15,7 @@ if { [info exists ENDIAN] } {
    set  _ENDIAN little
 }
 
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
    set _CPUTAPID 0x40700f0f
@@ -28,11 +28,11 @@ target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAM
 
 $_TARGETNAME configure -event reset-start {
        # start off real slow when we're running off internal RC oscillator
-       jtag_khz 10
+       adapter_khz 32
 }
 
 proc peek32 {address} {
-       ocd_mem2array t 32 $address 1
+       mem2array t 32 $address 1
        return $t(0)
 }
 
@@ -76,6 +76,10 @@ $_TARGETNAME configure -event reset-init {
        wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}  
 
        echo "Master clock ok."
+       
+       # Now that we're up and running, crank up speed!
+       global post_reset_khz ; adapter_khz $post_reset_khz
+       
        echo "Configuring the SDRAM controller..."
 
        # Configure EBI Chip select for SDRAM
@@ -149,10 +153,6 @@ $_TARGETNAME configure -event reset-init {
        mww 0xffffef00 0x3
        
        echo "SDRAM configuration ok."
-
-       # Now that we're up and running, crank up speed!
-       global post_reset_khz
-       jtag_khz $post_reset_khz
 }
 
 $_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0