* Intel XScale® Core Developer’s Manual, January 2004
* Order Number: 273473-002
* This has a chapter detailing debug facilities, and punts some
- * details to chip-specific microarchitecture documentats.
+ * details to chip-specific microarchitecture documents.
*
* Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
* Document Number: 273539-005
static int xscale_read_trace(target_t *);
+/* This XScale "debug handler" is loaded into the processor's
+ * mini-ICache, which is 2K of code writable only via JTAG.
+ *
+ * FIXME the OpenOCD "bin2char" utility currently doesn't handle
+ * binary files cleanly. It's string oriented, and terminates them
+ * with a NUL character. Better would be to generate the constants
+ * and let other code decide names, scoping, and other housekeeping.
+ */
+static /* unsigned const char xscale_debug_handler[] = ... */
+#include "xscale_debug.h"
+
static char *const xscale_reg_list[] =
{
"XSCALE_MAINID", /* 0 */
if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
{
scan_field_t field;
+ uint8_t scratch[4];
+ memset(&field, 0, sizeof field);
field.tap = tap;
field.num_bits = tap->ir_length;
- field.out_value = calloc(CEIL(field.num_bits, 8), 1);
+ field.out_value = scratch;
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
- uint8_t tmp[4];
- field.in_value = tmp;
-
jtag_add_ir_scan(1, &field, jtag_get_end_state());
-
- /* FIX!!!! isn't this check superfluous? verify_ircapture handles this? */
- jtag_check_value_mask(&field, tap->expected, tap->expected_mask);
-
- free(field.out_value);
}
return ERROR_OK;
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
-
int retval;
-
scan_field_t fields[3];
uint8_t field0 = 0x0;
uint8_t field0_check_value = 0x2;
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
+ memset(&fields, 0, sizeof fields);
+
fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0;
fields[1].tap = target->tap;
fields[1].num_bits = 32;
- fields[1].out_value = NULL;
fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
fields[2].tap = target->tap;
uint8_t field2_check_mask = 0x1;
int words_done = 0;
int words_scheduled = 0;
-
int i;
path[0] = TAP_DRSELECT;
path[1] = TAP_DRCAPTURE;
path[2] = TAP_DRSHIFT;
+ memset(&fields, 0, sizeof fields);
+
fields[0].tap = target->tap;
fields[0].num_bits = 3;
- fields[0].out_value = NULL;
- fields[0].in_value = NULL;
fields[0].check_value = &field0_check_value;
fields[0].check_mask = &field0_check_mask;
fields[1].tap = target->tap;
fields[1].num_bits = 32;
- fields[1].out_value = NULL;
- fields[1].check_value = NULL;
- fields[1].check_mask = NULL;
fields[2].tap = target->tap;
fields[2].num_bits = 1;
- fields[2].out_value = NULL;
- fields[2].in_value = NULL;
fields[2].check_value = &field2_check_value;
fields[2].check_mask = &field2_check_mask;
xscale_common_t *xscale = armv4_5->arch_info;
tap_state_t path[3];
tap_state_t noconsume_path[6];
-
int retval;
struct timeval timeout, now;
-
scan_field_t fields[3];
uint8_t field0_in = 0x0;
uint8_t field0_check_value = 0x2;
noconsume_path[4] = TAP_DREXIT2;
noconsume_path[5] = TAP_DRSHIFT;
+ memset(&fields, 0, sizeof fields);
+
fields[0].tap = target->tap;
fields[0].num_bits = 3;
- fields[0].out_value = NULL;
fields[0].in_value = &field0_in;
fields[1].tap = target->tap;
fields[1].num_bits = 32;
- fields[1].out_value = NULL;
fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
fields[2].tap = target->tap;
fields[2].num_bits = 1;
- fields[2].out_value = NULL;
uint8_t tmp;
fields[2].in_value = &tmp;
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
-
int retval;
struct timeval timeout, now;
-
scan_field_t fields[3];
uint8_t field0_out = 0x0;
uint8_t field0_in = 0x0;
xscale_jtag_set_instr(target->tap, XSCALE_DBGRX);
+ memset(&fields, 0, sizeof fields);
+
fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0_out;
fields[1].tap = target->tap;
fields[1].num_bits = 32;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
- fields[1].in_value = NULL;
fields[2].tap = target->tap;
fields[2].num_bits = 1;
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
-
int retval;
-
scan_field_t fields[3];
uint8_t field0 = 0x0;
uint8_t field0_check_value = 0x2;
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
+ memset(&fields, 0, sizeof fields);
+
fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0;
fields[1].tap = target->tap;
fields[1].num_bits = 32;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
- fields[1].in_value = NULL;
fields[2].tap = target->tap;
fields[2].num_bits = 1;
/* virtual address of desired cache line */
buf_set_u32(packet, 0, 27, va >> 5);
+ memset(&fields, 0, sizeof fields);
+
fields[0].tap = target->tap;
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
- fields[0].in_value = NULL;
fields[1].tap = target->tap;
fields[1].num_bits = 27;
fields[1].out_value = packet;
- fields[1].in_value = NULL;
jtag_add_dr_scan(2, fields, jtag_get_end_state());
/* virtual address of desired cache line */
buf_set_u32(packet, 0, 27, va >> 5);
+ memset(&fields, 0, sizeof fields);
+
fields[0].tap = target->tap;
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
- fields[0].in_value = NULL;
fields[1].tap = target->tap;
fields[1].num_bits = 27;
fields[1].out_value = packet;
- fields[1].in_value = NULL;
jtag_add_dr_scan(2, fields, jtag_get_end_state());
static int xscale_poll(target_t *target)
{
int retval = ERROR_OK;
- armv4_5_common_t *armv4_5 = target->arch_info;
- xscale_common_t *xscale = armv4_5->arch_info;
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING))
{
{
/* there's data to read from the tx register, we entered debug state */
- xscale->handler_running = 1;
-
target->state = TARGET_HALTED;
/* process debug entry, fetching current mode regs */
LOG_DEBUG("target resumed");
- xscale->handler_running = 1;
-
return ERROR_OK;
}
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
-
- fileio_t debug_handler;
- uint32_t address;
- uint32_t binary_size;
-
- uint32_t buf_cnt;
- uint32_t i;
- int retval;
-
breakpoint_t *breakpoint = target->breakpoints;
LOG_DEBUG("-");
breakpoint = breakpoint->next;
}
- if (!xscale->handler_installed)
+ armv4_5_invalidate_core_regs(target);
+
+ /* FIXME mark hardware watchpoints got unset too. Also,
+ * at least some of the XScale registers are invalid...
+ */
+
+ /*
+ * REVISIT: *assumes* we had a SRST+TRST reset so the mini-icache
+ * contents got invalidated. Safer to force that, so writing new
+ * contents can't ever fail..
+ */
{
+ uint32_t address;
+ unsigned buf_cnt;
+ const uint8_t *buffer = xscale_debug_handler;
+ int retval;
+
/* release SRST */
jtag_add_reset(0, 0);
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
xscale_write_dcsr(target, 1, 0);
- /* Load debug handler */
- if (fileio_open(&debug_handler, "xscale/debug_handler.bin", FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
- {
- return ERROR_OK;
- }
-
- if ((binary_size = debug_handler.size) % 4)
- {
- LOG_ERROR("debug_handler.bin: size not a multiple of 4");
- exit(-1);
- }
-
- if (binary_size > 0x800)
- {
- LOG_ERROR("debug_handler.bin: larger than 2kb");
- exit(-1);
- }
-
- binary_size = CEIL(binary_size, 32) * 32;
-
+ /* Load the debug handler into the mini-icache. Since
+ * it's using halt mode (not monitor mode), it runs in
+ * "Special Debug State" for access to registers, memory,
+ * coprocessors, trace data, etc.
+ */
address = xscale->handler_address;
- while (binary_size > 0)
+ for (unsigned binary_size = sizeof xscale_debug_handler - 1;
+ binary_size > 0;
+ binary_size -= buf_cnt, buffer += buf_cnt)
{
uint32_t cache_line[8];
- uint8_t buffer[32];
+ unsigned i;
- if ((retval = fileio_read(&debug_handler, 32, buffer, &buf_cnt)) != ERROR_OK)
- {
-
- }
+ buf_cnt = binary_size;
+ if (buf_cnt > 32)
+ buf_cnt = 32;
for (i = 0; i < buf_cnt; i += 4)
{
/* only load addresses other than the reset vectors */
if ((address % 0x400) != 0x0)
{
- xscale_load_ic(target, address, cache_line);
+ retval = xscale_load_ic(target, address,
+ cache_line);
+ if (retval != ERROR_OK)
+ return retval;
}
address += buf_cnt;
- binary_size -= buf_cnt;
};
- xscale_load_ic(target, 0x0, xscale->low_vectors);
- xscale_load_ic(target, 0xffff0000, xscale->high_vectors);
+ retval = xscale_load_ic(target, 0x0,
+ xscale->low_vectors);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = xscale_load_ic(target, 0xffff0000,
+ xscale->high_vectors);
+ if (retval != ERROR_OK)
+ return retval;
jtag_add_runtest(30, jtag_set_end_state(TAP_IDLE));
/* resume the target */
xscale_resume(target, 1, 0x0, 1, 0);
}
-
- fileio_close(&debug_handler);
- }
- else
- {
- jtag_add_reset(0, 0);
}
return ERROR_OK;
return ERROR_OK;
}
-static int xscale_quit(void)
-{
- jtag_add_runtest(100, TAP_RESET);
- return ERROR_OK;
-}
-
static int xscale_init_arch_info(target_t *target,
xscale_common_t *xscale, jtag_tap_t *tap, const char *variant)
{
}
/* the debug handler isn't installed (and thus not running) at this time */
- xscale->handler_installed = 0;
- xscale->handler_running = 0;
xscale->handler_address = 0xfe000800;
/* clear the vectors we keep locally for reference */
{
xscale_common_t *xscale;
+ if (sizeof xscale_debug_handler - 1 > 0x800) {
+ LOG_ERROR("debug_handler.bin: larger than 2kb");
+ return ERROR_FAIL;
+ }
+
xscale = calloc(1, sizeof(*xscale));
if (!xscale)
return ERROR_FAIL;
.register_commands = xscale_register_commands,
.target_create = xscale_target_create,
.init_target = xscale_init_target,
- .quit = xscale_quit,
.virt2phys = xscale_virt2phys,
.mmu = xscale_mmu
Code Review / openocd.git / blobdiff