#include "config.h"
#endif
+#include "breakpoints.h"
#include "xscale.h"
#include "target_type.h"
-#include "arm7_9_common.h"
+#include "arm_jtag.h"
#include "arm_simulator.h"
#include "arm_disassembler.h"
#include "time_support.h"
+#include "register.h"
#include "image.h"
{-1, NULL}, /* TXRXCTRL implicit access via JTAG */
};
-static int xscale_reg_arch_type = -1;
-
/* convenience wrapper to access XScale specific registers */
static int xscale_set_reg_u32(struct reg *reg, uint32_t value)
{
break;
default:
LOG_ERROR("BUG: size neither 4, 2 nor 1");
- exit(-1);
+ return ERROR_INVALID_ARGUMENTS;
}
jtag_add_dr_out(target->tap,
3,
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
LOG_ERROR("BUG: called for a non-ARMv4/5 target");
- exit(-1);
+ return ERROR_INVALID_ARGUMENTS;
}
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
*buffer++ = buf32[i] & 0xff;
break;
default:
- LOG_ERROR("should never get here");
- exit(-1);
+ LOG_ERROR("invalid read size");
+ return ERROR_INVALID_ARGUMENTS;
}
}
struct xscale_common *xscale = target_to_xscale(target);
int i;
int section = -1;
- uint32_t size_read;
+ size_t size_read;
uint32_t opcode;
int retval;
return ERROR_OK;
}
+static const struct reg_arch_type xscale_reg_type = {
+ .get = xscale_get_reg,
+ .set = xscale_set_reg,
+};
+
static void xscale_build_reg_cache(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
armv4_5->core_cache = (*cache_p);
- /* register a register arch-type for XScale dbg registers only once */
- if (xscale_reg_arch_type == -1)
- xscale_reg_arch_type = register_reg_arch_type(xscale_get_reg, xscale_set_reg);
-
(*cache_p)->next = malloc(sizeof(struct reg_cache));
cache_p = &(*cache_p)->next;
(*cache_p)->reg_list[i].valid = 0;
(*cache_p)->reg_list[i].size = 32;
(*cache_p)->reg_list[i].arch_info = &arch_info[i];
- (*cache_p)->reg_list[i].arch_type = xscale_reg_arch_type;
+ (*cache_p)->reg_list[i].type = &xscale_reg_type;
arch_info[i] = xscale_reg_arch_info[i];
arch_info[i].target = target;
}
int retval;
uint32_t handler_address;
- if (argc < 2)
+ if (CMD_ARGC < 2)
{
LOG_ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
return ERROR_OK;
}
- if ((target = get_target(args[0])) == NULL)
+ if ((target = get_target(CMD_ARGV[0])) == NULL)
{
- LOG_ERROR("target '%s' not defined", args[0]);
+ LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
return ERROR_FAIL;
}
if (retval != ERROR_OK)
return retval;
- COMMAND_PARSE_NUMBER(u32, args[1], handler_address);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], handler_address);
if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) ||
((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800)))
int retval;
uint32_t cache_clean_address;
- if (argc < 2)
+ if (CMD_ARGC < 2)
{
return ERROR_COMMAND_SYNTAX_ERROR;
}
- target = get_target(args[0]);
+ target = get_target(CMD_ARGV[0]);
if (target == NULL)
{
- LOG_ERROR("target '%s' not defined", args[0]);
+ LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
return ERROR_FAIL;
}
xscale = target_to_xscale(target);
if (retval != ERROR_OK)
return retval;
- COMMAND_PARSE_NUMBER(u32, args[1], cache_clean_address);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cache_clean_address);
if (cache_clean_address & 0xffff)
{
return ERROR_OK;
}
- if (argc >= 1)
+ if (CMD_ARGC >= 1)
{
- if (strcmp("enable", args[0]) == 0)
+ if (strcmp("enable", CMD_ARGV[0]) == 0)
{
xscale_enable_mmu_caches(target, 1, 0, 0);
xscale->armv4_5_mmu.mmu_enabled = 1;
}
- else if (strcmp("disable", args[0]) == 0)
+ else if (strcmp("disable", CMD_ARGV[0]) == 0)
{
xscale_disable_mmu_caches(target, 1, 0, 0);
xscale->armv4_5_mmu.mmu_enabled = 0;
else if (strcmp(CMD_NAME, "dcache") == 0)
dcache = 1;
- if (argc >= 1)
+ if (CMD_ARGC >= 1)
{
- if (strcmp("enable", args[0]) == 0)
+ if (strcmp("enable", CMD_ARGV[0]) == 0)
{
xscale_enable_mmu_caches(target, 0, dcache, icache);
else if (dcache)
xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 1;
}
- else if (strcmp("disable", args[0]) == 0)
+ else if (strcmp("disable", CMD_ARGV[0]) == 0)
{
xscale_disable_mmu_caches(target, 0, dcache, icache);
if (retval != ERROR_OK)
return retval;
- if (argc < 1)
+ if (CMD_ARGC < 1)
{
command_print(cmd_ctx, "usage: xscale vector_catch [mask]");
}
else
{
- COMMAND_PARSE_NUMBER(u8, args[0], xscale->vector_catch);
+ COMMAND_PARSE_NUMBER(u8, CMD_ARGV[0], xscale->vector_catch);
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 8, xscale->vector_catch);
xscale_write_dcsr(target, -1, -1);
}
if (retval != ERROR_OK)
return retval;
- if (argc == 0) /* print current settings */
+ if (CMD_ARGC == 0) /* print current settings */
{
int idx;
return ERROR_OK;
}
- if (argc != 3)
+ if (CMD_ARGC != 3)
err = 1;
else
{
int idx;
- COMMAND_PARSE_NUMBER(int, args[1], idx);
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], idx);
uint32_t vec;
- COMMAND_PARSE_NUMBER(u32, args[2], vec);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], vec);
if (idx < 1 || idx >= 8)
err = 1;
- if (!err && strcmp(args[0], "low") == 0)
+ if (!err && strcmp(CMD_ARGV[0], "low") == 0)
{
xscale->static_low_vectors_set |= (1<<idx);
xscale->static_low_vectors[idx] = vec;
}
- else if (!err && (strcmp(args[0], "high") == 0))
+ else if (!err && (strcmp(CMD_ARGV[0], "high") == 0))
{
xscale->static_high_vectors_set |= (1<<idx);
xscale->static_high_vectors[idx] = vec;
return ERROR_OK;
}
- if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
+ if ((CMD_ARGC >= 1) && (strcmp("enable", CMD_ARGV[0]) == 0))
{
struct xscale_trace_data *td, *next_td;
xscale->trace.buffer_enabled = 1;
}
xscale->trace.data = NULL;
}
- else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
+ else if ((CMD_ARGC >= 1) && (strcmp("disable", CMD_ARGV[0]) == 0))
{
xscale->trace.buffer_enabled = 0;
}
- if ((argc >= 2) && (strcmp("fill", args[1]) == 0))
+ if ((CMD_ARGC >= 2) && (strcmp("fill", CMD_ARGV[1]) == 0))
{
uint32_t fill = 1;
- if (argc >= 3)
- COMMAND_PARSE_NUMBER(u32, args[2], fill);
+ if (CMD_ARGC >= 3)
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], fill);
xscale->trace.buffer_fill = fill;
}
- else if ((argc >= 2) && (strcmp("wrap", args[1]) == 0))
+ else if ((CMD_ARGC >= 2) && (strcmp("wrap", CMD_ARGV[1]) == 0))
{
xscale->trace.buffer_fill = -1;
}
struct xscale_common *xscale = target_to_xscale(target);
int retval;
- if (argc < 1)
+ if (CMD_ARGC < 1)
{
command_print(cmd_ctx, "usage: xscale trace_image <file> [base address] [type]");
return ERROR_OK;
xscale->trace.image->start_address_set = 0;
/* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
- if (argc >= 2)
+ if (CMD_ARGC >= 2)
{
xscale->trace.image->base_address_set = 1;
- COMMAND_PARSE_NUMBER(int, args[1], xscale->trace.image->base_address);
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], xscale->trace.image->base_address);
}
else
{
xscale->trace.image->base_address_set = 0;
}
- if (image_open(xscale->trace.image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
+ if (image_open(xscale->trace.image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK)
{
free(xscale->trace.image);
xscale->trace.image = NULL;
return ERROR_OK;
}
- if (argc < 1)
+ if (CMD_ARGC < 1)
{
command_print(cmd_ctx, "usage: xscale dump_trace <file>");
return ERROR_OK;
return ERROR_OK;
}
- if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
+ if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
{
return ERROR_OK;
}
}
uint32_t reg_no = 0;
struct reg *reg = NULL;
- if (argc > 0)
+ if (CMD_ARGC > 0)
{
- COMMAND_PARSE_NUMBER(u32, args[0], reg_no);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg_no);
/*translate from xscale cp15 register no to openocd register*/
switch (reg_no)
{
reg = &xscale->reg_cache->reg_list[reg_no];
}
- if (argc == 1)
+ if (CMD_ARGC == 1)
{
uint32_t value;
value = buf_get_u32(reg->value, 0, 32);
command_print(cmd_ctx, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size), value);
}
- else if (argc == 2)
+ else if (CMD_ARGC == 2)
{
uint32_t value;
- COMMAND_PARSE_NUMBER(u32, args[1], value);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
/* send CP write request (command 0x41) */
xscale_send_u32(target, 0x41);
.read_memory = xscale_read_memory,
.write_memory = xscale_write_memory,
.bulk_write_memory = xscale_bulk_write_memory,
- .checksum_memory = arm7_9_checksum_memory,
- .blank_check_memory = arm7_9_blank_check_memory,
+
+ .checksum_memory = arm_checksum_memory,
+ .blank_check_memory = arm_blank_check_memory,
.run_algorithm = armv4_5_run_algorithm,