int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int xscale_quit();
-int xscale_arch_state(struct target_s *target, char *buf, int buf_size);
-enum target_state xscale_poll(target_t *target);
+int xscale_arch_state(struct target_s *target);
+int xscale_poll(target_t *target);
int xscale_halt(target_t *target);
int xscale_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
int xscale_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
field.in_value = NULL;
jtag_set_check_value(&field, device->expected, device->expected_mask, NULL);
- jtag_add_ir_scan(1, &field, -1, NULL);
+ jtag_add_ir_scan(1, &field, -1);
free(field.out_value);
}
return ERROR_OK;
}
-int xscale_jtag_callback(enum jtag_event event, void *priv)
-{
- switch (event)
- {
- case JTAG_TRST_ASSERTED:
- break;
- case JTAG_TRST_RELEASED:
- break;
- case JTAG_SRST_ASSERTED:
- break;
- case JTAG_SRST_RELEASED:
- break;
- default:
- WARNING("unhandled JTAG event");
- }
-
- return ERROR_OK;
-}
-
int xscale_read_dcsr(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL;
-
-
fields[2].device = xscale->jtag_info.chain_pos;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
fields[2].in_value = NULL;
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
- jtag_add_dr_scan(3, fields, -1, NULL);
+ jtag_add_dr_scan(3, fields, -1);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
jtag_add_end_state(TAP_RTI);
- jtag_add_dr_scan(3, fields, -1, NULL);
+ jtag_add_dr_scan(3, fields, -1);
- return ERROR_OK;
+ /* DANGER!!! this must be here. It will make sure that the arguments
+ * to jtag_set_check_value() does not go out of scope! */
+ return jtag_execute_queue();
}
int xscale_receive(target_t *target, u32 *buffer, int num_words)
{
- int retval = ERROR_OK;
+ if (num_words==0)
+ return ERROR_INVALID_ARGUMENTS;
+
+ int retval=ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
fields[0].num_bits = 3;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
- /* fields[0].in_value = field0; */
+ fields[0].in_value = NULL;
jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
fields[1].device = xscale->jtag_info.chain_pos;
jtag_add_end_state(TAP_RTI);
xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx);
- jtag_add_runtest(1, -1);
+ jtag_add_runtest(1, -1); /* ensures that we're in the TAP_RTI state as the above could be a no-op */
/* repeat until all words have been collected */
- int attempts = 0;
+ int attempts=0;
while (words_done < num_words)
{
/* schedule reads */
fields[1].in_handler_priv = (u8*)&field1[i];
jtag_add_pathmove(3, path);
- jtag_add_dr_scan(3, fields, TAP_RTI, NULL);
+ jtag_add_dr_scan(3, fields, TAP_RTI);
words_scheduled++;
}
words_scheduled--;
}
}
- if (words_scheduled == 0)
+ if (words_scheduled==0)
{
- if (attempts++ == 1000)
+ if (attempts++==1000)
{
ERROR("Failed to receiving data from debug handler after 1000 attempts");
- retval = ERROR_JTAG_QUEUE_FAILED;
+ retval=ERROR_TARGET_TIMEOUT;
break;
}
}
noconsume_path[6] = TAP_SDS;
noconsume_path[7] = TAP_CD;
noconsume_path[8] = TAP_SD;
-
+
fields[0].device = xscale->jtag_info.chain_pos;
fields[0].num_bits = 3;
fields[0].out_value = NULL;
gettimeofday(&timeout, NULL);
timeval_add_time(&timeout, 5, 0);
- do
+ for (;;)
{
/* if we want to consume the register content (i.e. clear TX_READY),
* we have to go straight from Capture-DR to Shift-DR
else
jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path);
- jtag_add_dr_scan(3, fields, TAP_RTI, NULL);
+ jtag_add_dr_scan(3, fields, TAP_RTI);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
ERROR("time out reading TX register");
return ERROR_TARGET_TIMEOUT;
}
- } while ((!(field0_in & 1)) && consume);
+ if (!((!(field0_in & 1)) && consume))
+ {
+ break;
+ }
+ usleep(500*1000); /* avoid flooding the logs */
+ }
if (!(field0_in & 1))
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
/* poll until rx_read is low */
DEBUG("polling RX");
- do
+ for (;;)
{
- jtag_add_dr_scan(3, fields, TAP_RTI, NULL);
+ jtag_add_dr_scan(3, fields, TAP_RTI);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
ERROR("time out writing RX register");
return ERROR_TARGET_TIMEOUT;
}
- } while (field0_in & 1);
+ if (!(field0_in & 1))
+ break;
+ usleep(500*1000); /* wait 500ms to avoid flooding the logs */
+ }
/* set rx_valid */
field2 = 0x1;
- jtag_add_dr_scan(3, fields, TAP_RTI, NULL);
+ jtag_add_dr_scan(3, fields, TAP_RTI);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
scan_field_t fields[3];
u8 field0_out = 0x0;
- u8 field0_in = 0x0;
u8 field0_check_value = 0x2;
u8 field0_check_mask = 0x6;
u8 field2 = 0x1;
fields[0].num_bits = 3;
fields[0].out_value = &field0_out;
fields[0].out_mask = NULL;
- fields[0].in_value = &field0_in;
- jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
+ fields[0].in_handler = NULL;
+ fields[0].in_value = NULL;
+ if (!xscale->fast_memory_access)
+ {
+ jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
+ }
fields[1].device = xscale->jtag_info.chain_pos;
fields[1].num_bits = 32;
fields[2].out_value = &field2;
fields[2].out_mask = NULL;
fields[2].in_value = NULL;
- jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
-
- while (done_count++ < count)
+ fields[2].in_handler = NULL;
+ if (!xscale->fast_memory_access)
{
- /* extract sized element from target-endian buffer, and put it
- * into little-endian output buffer
- */
- switch (size)
+ jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
+ }
+
+ if (size==4)
+ {
+ int endianness = target->endianness;
+ while (done_count++ < count)
{
- case 4:
- buf_set_u32(output, 0, 32, target_buffer_get_u32(target, buffer));
- break;
- case 2:
- buf_set_u32(output, 0, 32, target_buffer_get_u16(target, buffer));
- break;
- case 1:
- output[0] = *buffer;
- break;
- default:
- ERROR("BUG: size neither 4, 2 nor 1");
- exit(-1);
+ if (endianness == TARGET_LITTLE_ENDIAN)
+ {
+ output[0]=buffer[0];
+ output[1]=buffer[1];
+ output[2]=buffer[2];
+ output[3]=buffer[3];
+ } else
+ {
+ output[0]=buffer[3];
+ output[1]=buffer[2];
+ output[2]=buffer[1];
+ output[3]=buffer[0];
+ }
+ jtag_add_dr_scan(3, fields, TAP_RTI);
+ buffer += size;
}
+
+ } else
+ {
+ while (done_count++ < count)
+ {
+ /* extract sized element from target-endian buffer, and put it
+ * into little-endian output buffer
+ */
+ switch (size)
+ {
+ case 2:
+ buf_set_u32(output, 0, 32, target_buffer_get_u16(target, buffer));
+ break;
+ case 1:
+ output[0] = *buffer;
+ break;
+ default:
+ ERROR("BUG: size neither 4, 2 nor 1");
+ exit(-1);
+ }
- jtag_add_dr_scan(3, fields, TAP_RTI, NULL);
- buffer += size;
+ jtag_add_dr_scan(3, fields, TAP_RTI);
+ buffer += size;
+ }
+
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
fields[2].in_value = NULL;
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
- jtag_add_dr_scan(3, fields, -1, NULL);
+ jtag_add_dr_scan(3, fields, -1);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- jtag_add_dr_scan(2, fields, -1, NULL);
+ jtag_add_dr_scan(2, fields, -1);
fields[0].num_bits = 32;
fields[0].out_value = packet;
{
buf_set_u32(packet, 0, 32, buffer[word]);
cmd = parity(*((u32*)packet));
- jtag_add_dr_scan(2, fields, -1, NULL);
+ jtag_add_dr_scan(2, fields, -1);
}
jtag_execute_queue();
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
- jtag_add_dr_scan(2, fields, -1, NULL);
+ jtag_add_dr_scan(2, fields, -1);
return ERROR_OK;
}
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
int i;
+ int retval;
u32 low_reset_branch, high_reset_branch;
}
else
{
- if (target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]) != ERROR_OK)
+ retval=target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
+ if (retval == ERROR_TARGET_TIMEOUT)
+ return retval;
+ if (retval!=ERROR_OK)
{
+ /* Some of these reads will fail as part of normal execution */
xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
}
}
}
else
{
- if (target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]) != ERROR_OK)
+ retval=target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
+ if (retval == ERROR_TARGET_TIMEOUT)
+ return retval;
+ if (retval!=ERROR_OK)
{
+ /* Some of these reads will fail as part of normal execution */
xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
}
}
return ERROR_OK;
}
-int xscale_arch_state(struct target_s *target, char *buf, int buf_size)
+int xscale_arch_state(struct target_s *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
exit(-1);
}
- snprintf(buf, buf_size,
- "target halted in %s state due to %s, current mode: %s\n"
+ USER("target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8x pc: 0x%8.8x\n"
"MMU: %s, D-Cache: %s, I-Cache: %s"
"%s",
return ERROR_OK;
}
-enum target_state xscale_poll(target_t *target)
+int xscale_poll(target_t *target)
{
- int retval;
+ int retval=ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING))
{
+ enum target_state previous_state = target->state;
if ((retval = xscale_read_tx(target, 0)) == ERROR_OK)
{
- enum target_state previous_state = target->state;
/* there's data to read from the tx register, we entered debug state */
xscale->handler_running = 1;
target->state = TARGET_HALTED;
/* process debug entry, fetching current mode regs */
- if ((retval = xscale_debug_entry(target)) != ERROR_OK)
- return retval;
-
- /* debug_entry could have overwritten target state (i.e. immediate resume)
- * don't signal event handlers in that case
- */
- if (target->state != TARGET_HALTED)
- return target->state;
-
- /* if target was running, signal that we halted
- * otherwise we reentered from debug execution */
- if (previous_state == TARGET_RUNNING)
- target_call_event_callbacks(target, TARGET_EVENT_HALTED);
- else
- target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
+ retval = xscale_debug_entry(target);
}
else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
{
- ERROR("error while polling TX register");
- return retval;
+ USER("error while polling TX register, reset CPU");
+ /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
+ target->state = TARGET_HALTED;
}
+
+ /* debug_entry could have overwritten target state (i.e. immediate resume)
+ * don't signal event handlers in that case
+ */
+ if (target->state != TARGET_HALTED)
+ return ERROR_OK;
+
+ /* if target was running, signal that we halted
+ * otherwise we reentered from debug execution */
+ if (previous_state == TARGET_RUNNING)
+ target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+ else
+ target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
}
- return target->state;
+ return retval;
}
int xscale_debug_entry(target_t *target)
u32 pc;
u32 buffer[10];
int i;
+ int retval;
u32 moe;
/* clear external dbg break (will be written on next DCSR read) */
xscale->external_debug_break = 0;
- xscale_read_dcsr(target);
-
+ if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
+ return retval;
+
/* get r0, pc, r1 to r7 and cpsr */
- xscale_receive(target, buffer, 10);
+ if ((retval=xscale_receive(target, buffer, 10))!=ERROR_OK)
+ return retval;
/* move r0 from buffer to register cache */
buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]);
if (target->state == TARGET_HALTED)
{
WARNING("target was already halted");
- return ERROR_TARGET_ALREADY_HALTED;
+ return ERROR_OK;
}
else if (target->state == TARGET_UNKNOWN)
{
}
/* update vector tables */
- xscale_update_vectors(target);
+ if ((retval=xscale_update_vectors(target))!=ERROR_OK)
+ return retval;
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current)
xscale_write_dcsr(target, 1, 0);
/* Load debug handler */
- if (fileio_open(&debug_handler, PKGLIBDIR "/xscale/debug_handler.bin", FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
+ if (fileio_open(&debug_handler, "xscale/debug_handler.bin", FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
{
- ERROR("file open error: %s", debug_handler.error_str);
return ERROR_OK;
}
if ((retval = fileio_read(&debug_handler, 32, buffer, &buf_cnt)) != ERROR_OK)
{
- ERROR("reading debug handler failed: %s", debug_handler.error_str);
+
}
for (i = 0; i < buf_cnt; i += 4)
xscale_common_t *xscale = armv4_5->arch_info;
u32 *buf32;
int i;
+ int retval;
DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
return ERROR_TARGET_UNALIGNED_ACCESS;
/* send memory read request (command 0x1n, n: access size) */
- xscale_send_u32(target, 0x10 | size);
+ if ((retval=xscale_send_u32(target, 0x10 | size))!=ERROR_OK)
+ return retval;
/* send base address for read request */
- xscale_send_u32(target, address);
+ if ((retval=xscale_send_u32(target, address))!=ERROR_OK)
+ return retval;
/* send number of requested data words */
- xscale_send_u32(target, count);
+ if ((retval=xscale_send_u32(target, count))!=ERROR_OK)
+ return retval;
/* receive data from target (count times 32-bit words in host endianness) */
buf32 = malloc(4 * count);
- xscale_receive(target, buf32, count);
+ if ((retval=xscale_receive(target, buf32, count))!=ERROR_OK)
+ return retval;
/* extract data from host-endian buffer into byte stream */
for (i = 0; i < count; i++)
free(buf32);
/* examine DCSR, to see if Sticky Abort (SA) got set */
- xscale_read_dcsr(target);
+ if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
+ return retval;
if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
{
/* clear SA bit */
- xscale_send_u32(target, 0x60);
+ if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK)
+ return retval;
return ERROR_TARGET_DATA_ABORT;
}
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
+ int retval;
DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
return ERROR_TARGET_UNALIGNED_ACCESS;
/* send memory write request (command 0x2n, n: access size) */
- xscale_send_u32(target, 0x20 | size);
+ if ((retval=xscale_send_u32(target, 0x20 | size))!=ERROR_OK)
+ return retval;
/* send base address for read request */
- xscale_send_u32(target, address);
+ if ((retval=xscale_send_u32(target, address))!=ERROR_OK)
+ return retval;
/* send number of requested data words to be written*/
- xscale_send_u32(target, count);
+ if ((retval=xscale_send_u32(target, count))!=ERROR_OK)
+ return retval;
/* extract data from host-endian buffer into byte stream */
#if 0
}
}
#endif
- xscale_send(target, buffer, count, size);
+ if ((retval=xscale_send(target, buffer, count, size))!=ERROR_OK)
+ return retval;
/* examine DCSR, to see if Sticky Abort (SA) got set */
- xscale_read_dcsr(target);
+ if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
+ return retval;
if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
{
/* clear SA bit */
- xscale_send_u32(target, 0x60);
+ if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK)
+ return retval;
return ERROR_TARGET_DATA_ABORT;
}
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
- u8 enable = 0;
+ u8 enable=0;
reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
u32 dbcon_value = buf_get_u32(dbcon->value, 0, 32);
/* prepare JTAG information for the new target */
xscale->jtag_info.chain_pos = chain_pos;
- jtag_register_event_callback(xscale_jtag_callback, target);
xscale->jtag_info.dbgrx = 0x02;
xscale->jtag_info.dbgtx = 0x10;
xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches;
xscale->armv4_5_mmu.has_tiny_pages = 1;
xscale->armv4_5_mmu.mmu_enabled = 0;
+
+ xscale->fast_memory_access = 0;
return ERROR_OK;
}
int chain_pos;
char *variant = NULL;
xscale_common_t *xscale = malloc(sizeof(xscale_common_t));
+ memset(xscale, 0, sizeof(*xscale));
if (argc < 5)
{
int domain;
u32 ap;
+
if ((retval = xscale_get_arch_pointers(target, &armv4_5, &xscale)) != ERROR_OK)
{
return retval;
{
return ret;
}
-
*physical = ret;
return ERROR_OK;
}
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
-
+
if (target->state != TARGET_HALTED)
{
ERROR("Target not halted");
return ERROR_TARGET_INVALID;
}
-
*enabled = xscale->armv4_5_mmu.mmu_enabled;
return ERROR_OK;
}
+
int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
if (image_open(xscale->trace.image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
{
- command_print(cmd_ctx, "image opening error: %s", xscale->trace.image->error_str);
free(xscale->trace.image);
xscale->trace.image = NULL;
return ERROR_OK;
if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
{
- command_print(cmd_ctx, "file open error: %s", file.error_str);
return ERROR_OK;
}
return ERROR_OK;
}
+int handle_xscale_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv4_5_common_t *armv4_5;
+ xscale_common_t *xscale;
+
+ if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
+ {
+ return ERROR_OK;
+ }
+
+ if (argc == 1)
+ {
+ if (strcmp("enable", args[0]) == 0)
+ {
+ xscale->fast_memory_access = 1;
+ }
+ else if (strcmp("disable", args[0]) == 0)
+ {
+ xscale->fast_memory_access = 0;
+ }
+ else
+ {
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+ } else if (argc!=0)
+ {
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ command_print(cmd_ctx, "fast memory access is %s", (xscale->fast_memory_access) ? "enabled" : "disabled");
+
+ return ERROR_OK;
+}
+
int xscale_register_commands(struct command_context_s *cmd_ctx)
{
command_t *xscale_cmd;
COMMAND_EXEC, "load image from <file> [base address]");
register_command(cmd_ctx, xscale_cmd, "cp15", xscale_handle_cp15, COMMAND_EXEC, "access coproc 15 <register> [value]");
+ register_command(cmd_ctx, xscale_cmd, "fast_memory_access", handle_xscale_fast_memory_access_command,
+ COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
+
armv4_5_register_commands(cmd_ctx);
Code Review / openocd.git / blobdiff