uint8_t field2_check_mask = 0x1;
jtag_set_end_state(TAP_DRPAUSE);
- xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
+ xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
- fields[0].tap = xscale->jtag_info.tap;
+ fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0;
uint8_t tmp;
fields[0].in_value = &tmp;
- fields[1].tap = xscale->jtag_info.tap;
+ fields[1].tap = target->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
- fields[2].tap = xscale->jtag_info.tap;
+ fields[2].tap = target->tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
uint8_t tmp2;
return ERROR_INVALID_ARGUMENTS;
int retval = ERROR_OK;
- armv4_5_common_t *armv4_5 = target->arch_info;
- xscale_common_t *xscale = armv4_5->arch_info;
-
tap_state_t path[3];
scan_field_t fields[3];
-
uint8_t *field0 = malloc(num_words * 1);
uint8_t field0_check_value = 0x2;
uint8_t field0_check_mask = 0x6;
path[1] = TAP_DRCAPTURE;
path[2] = TAP_DRSHIFT;
- fields[0].tap = xscale->jtag_info.tap;
+ fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].out_value = NULL;
fields[0].in_value = NULL;
fields[0].check_value = &field0_check_value;
fields[0].check_mask = &field0_check_mask;
- fields[1].tap = xscale->jtag_info.tap;
+ fields[1].tap = target->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].check_value = NULL;
fields[1].check_mask = NULL;
- fields[2].tap = xscale->jtag_info.tap;
+ fields[2].tap = target->tap;
fields[2].num_bits = 1;
fields[2].out_value = NULL;
fields[2].in_value = NULL;
fields[2].check_mask = &field2_check_mask;
jtag_set_end_state(TAP_IDLE);
- xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
+ xscale_jtag_set_instr(target->tap, XSCALE_DBGTX);
jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
/* repeat until all words have been collected */
jtag_set_end_state(TAP_IDLE);
- xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
+ xscale_jtag_set_instr(target->tap, XSCALE_DBGTX);
path[0] = TAP_DRSELECT;
path[1] = TAP_DRCAPTURE;
noconsume_path[4] = TAP_DREXIT2;
noconsume_path[5] = TAP_DRSHIFT;
- fields[0].tap = xscale->jtag_info.tap;
+ fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].out_value = NULL;
fields[0].in_value = &field0_in;
- fields[1].tap = xscale->jtag_info.tap;
+ fields[1].tap = target->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
- fields[2].tap = xscale->jtag_info.tap;
+ fields[2].tap = target->tap;
fields[2].num_bits = 1;
fields[2].out_value = NULL;
uint8_t tmp;
jtag_set_end_state(TAP_IDLE);
- xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx);
+ xscale_jtag_set_instr(target->tap, XSCALE_DBGRX);
- fields[0].tap = xscale->jtag_info.tap;
+ fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0_out;
fields[0].in_value = &field0_in;
- fields[1].tap = xscale->jtag_info.tap;
+ fields[1].tap = target->tap;
fields[1].num_bits = 32;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
fields[1].in_value = NULL;
- fields[2].tap = xscale->jtag_info.tap;
+ fields[2].tap = target->tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
uint8_t tmp;
/* send count elements of size byte to the debug handler */
static int xscale_send(target_t *target, uint8_t *buffer, int count, int size)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- xscale_common_t *xscale = armv4_5->arch_info;
uint32_t t[3];
int bits[3];
-
int retval;
-
int done_count = 0;
jtag_set_end_state(TAP_IDLE);
- xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx);
+ xscale_jtag_set_instr(target->tap, XSCALE_DBGRX);
bits[0]=3;
t[0]=0;
LOG_ERROR("BUG: size neither 4, 2 nor 1");
exit(-1);
}
- jtag_add_dr_out(xscale->jtag_info.tap,
+ jtag_add_dr_out(target->tap,
3,
bits,
t,
xscale->external_debug_break = ext_dbg_brk;
jtag_set_end_state(TAP_IDLE);
- xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
+ xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
- fields[0].tap = xscale->jtag_info.tap;
+ fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0;
uint8_t tmp;
fields[0].in_value = &tmp;
- fields[1].tap = xscale->jtag_info.tap;
+ fields[1].tap = target->tap;
fields[1].num_bits = 32;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
fields[1].in_value = NULL;
- fields[2].tap = xscale->jtag_info.tap;
+ fields[2].tap = target->tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
uint8_t tmp2;
/* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
static unsigned int parity (unsigned int v)
{
- unsigned int ov = v;
+ // unsigned int ov = v;
v ^= v >> 16;
v ^= v >> 8;
v ^= v >> 4;
v &= 0xf;
- LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
+ // LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
return (0x6996 >> v) & 1;
}
-static int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buffer[8])
+static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8])
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- xscale_common_t *xscale = armv4_5->arch_info;
uint8_t packet[4];
uint8_t cmd;
int word;
-
scan_field_t fields[2];
LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
+ /* LDIC into IR */
jtag_set_end_state(TAP_IDLE);
- xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
+ xscale_jtag_set_instr(target->tap, XSCALE_LDIC);
- /* CMD is b010 for Main IC and b011 for Mini IC */
- if (mini)
- buf_set_u32(&cmd, 0, 3, 0x3);
- else
- buf_set_u32(&cmd, 0, 3, 0x2);
-
- buf_set_u32(&cmd, 3, 3, 0x0);
+ /* CMD is b011 to load a cacheline into the Mini ICache.
+ * Loading into the main ICache is deprecated, and unused.
+ * It's followed by three zero bits, and 27 address bits.
+ */
+ buf_set_u32(&cmd, 0, 6, 0x3);
/* virtual address of desired cache line */
buf_set_u32(packet, 0, 27, va >> 5);
- fields[0].tap = xscale->jtag_info.tap;
+ fields[0].tap = target->tap;
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
fields[0].in_value = NULL;
- fields[1].tap = xscale->jtag_info.tap;
+ fields[1].tap = target->tap;
fields[1].num_bits = 27;
fields[1].out_value = packet;
fields[1].in_value = NULL;
jtag_add_dr_scan(2, fields, jtag_get_end_state());
+ /* rest of packet is a cacheline: 8 instructions, with parity */
fields[0].num_bits = 32;
fields[0].out_value = packet;
static int xscale_invalidate_ic_line(target_t *target, uint32_t va)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
- xscale_common_t *xscale = armv4_5->arch_info;
uint8_t packet[4];
uint8_t cmd;
-
scan_field_t fields[2];
jtag_set_end_state(TAP_IDLE);
- xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
+ xscale_jtag_set_instr(target->tap, XSCALE_LDIC);
/* CMD for invalidate IC line b000, bits [6:4] b000 */
buf_set_u32(&cmd, 0, 6, 0x0);
/* virtual address of desired cache line */
buf_set_u32(packet, 0, 27, va >> 5);
- fields[0].tap = xscale->jtag_info.tap;
+ fields[0].tap = target->tap;
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
fields[0].in_value = NULL;
- fields[1].tap = xscale->jtag_info.tap;
+ fields[1].tap = target->tap;
fields[1].num_bits = 27;
fields[1].out_value = packet;
fields[1].in_value = NULL;
xscale_invalidate_ic_line(target, 0x0);
xscale_invalidate_ic_line(target, 0xffff0000);
- xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
- xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
+ xscale_load_ic(target, 0x0, xscale->low_vectors);
+ xscale_load_ic(target, 0xffff0000, xscale->high_vectors);
return ERROR_OK;
}
* end up in T-L-R, which would reset JTAG
*/
jtag_set_end_state(TAP_IDLE);
- xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
+ xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR);
/* set Hold reset, Halt mode and Trap Reset */
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
xscale_write_dcsr(target, 1, 0);
/* select BYPASS, because having DCSR selected caused problems on the PXA27x */
- xscale_jtag_set_instr(xscale->jtag_info.tap, 0x7f);
+ xscale_jtag_set_instr(target->tap, 0x7f);
jtag_execute_queue();
/* assert reset */
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
-
- fileio_t debug_handler;
- uint32_t address;
- uint32_t binary_size;
-
- uint32_t buf_cnt;
- uint32_t i;
- int retval;
-
breakpoint_t *breakpoint = target->breakpoints;
LOG_DEBUG("-");
if (!xscale->handler_installed)
{
+ uint32_t address;
+ unsigned buf_cnt;
+ const uint8_t *buffer = xscale_debug_handler;
+ int retval;
+
/* release SRST */
jtag_add_reset(0, 0);
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
xscale_write_dcsr(target, 1, 0);
- /* Load debug handler */
- if (fileio_open(&debug_handler, "xscale/debug_handler.bin", FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
- {
- return ERROR_OK;
- }
-
- if ((binary_size = debug_handler.size) % 4)
- {
- LOG_ERROR("debug_handler.bin: size not a multiple of 4");
- exit(-1);
- }
-
- if (binary_size > 0x800)
- {
- LOG_ERROR("debug_handler.bin: larger than 2kb");
- exit(-1);
- }
-
- binary_size = CEIL(binary_size, 32) * 32;
-
+ /* Load the debug handler into the mini-icache. Since
+ * it's using halt mode (not monitor mode), it runs in
+ * "Special Debug State" for access to registers, memory,
+ * coprocessors, trace data, etc.
+ *
+ * REVISIT: *assumes* we've had a SRST+TRST reset so the
+ * mini-icache contents have been invalidated. Safest to
+ * force that, so writing new contents is reliable...
+ */
address = xscale->handler_address;
- while (binary_size > 0)
+ for (unsigned binary_size = xscale_debug_handler_size;
+ binary_size > 0;
+ binary_size -= buf_cnt, buffer += buf_cnt)
{
uint32_t cache_line[8];
- uint8_t buffer[32];
+ unsigned i;
- if ((retval = fileio_read(&debug_handler, 32, buffer, &buf_cnt)) != ERROR_OK)
- {
-
- }
+ buf_cnt = binary_size;
+ if (buf_cnt > 32)
+ buf_cnt = 32;
for (i = 0; i < buf_cnt; i += 4)
{
/* only load addresses other than the reset vectors */
if ((address % 0x400) != 0x0)
{
- xscale_load_ic(target, 1, address, cache_line);
+ retval = xscale_load_ic(target, address,
+ cache_line);
+ if (retval != ERROR_OK)
+ return retval;
}
address += buf_cnt;
- binary_size -= buf_cnt;
};
- xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
- xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
+ retval = xscale_load_ic(target, 0x0,
+ xscale->low_vectors);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = xscale_load_ic(target, 0xffff0000,
+ xscale->high_vectors);
+ if (retval != ERROR_OK)
+ return retval;
jtag_add_runtest(30, jtag_set_end_state(TAP_IDLE));
/* resume the target */
xscale_resume(target, 1, 0x0, 1, 0);
}
-
- fileio_close(&debug_handler);
}
else
{
static int xscale_init_target(struct command_context_s *cmd_ctx,
struct target_s *target)
{
+ xscale_build_reg_cache(target);
return ERROR_OK;
}
xscale->arch_info = NULL;
xscale->common_magic = XSCALE_COMMON_MAGIC;
- /* remember the variant (PXA25x, PXA27x, IXP42x, ...) */
- xscale->variant = strdup(variant);
-
- /* prepare JTAG information for the new target */
- xscale->jtag_info.tap = tap;
-
- xscale->jtag_info.dbgrx = 0x02;
- xscale->jtag_info.dbgtx = 0x10;
- xscale->jtag_info.dcsr = 0x09;
- xscale->jtag_info.ldic = 0x07;
+ /* we don't really *need* variant info ... */
+ if (variant) {
+ int ir_length = 0;
+
+ if (strcmp(variant, "pxa250") == 0
+ || strcmp(variant, "pxa255") == 0
+ || strcmp(variant, "pxa26x") == 0)
+ ir_length = 5;
+ else if (strcmp(variant, "pxa27x") == 0
+ || strcmp(variant, "ixp42x") == 0
+ || strcmp(variant, "ixp45x") == 0
+ || strcmp(variant, "ixp46x") == 0)
+ ir_length = 7;
+ else
+ LOG_WARNING("%s: unrecognized variant %s",
+ tap->dotted_name, variant);
- if ((strcmp(xscale->variant, "pxa250") == 0) ||
- (strcmp(xscale->variant, "pxa255") == 0) ||
- (strcmp(xscale->variant, "pxa26x") == 0))
- {
- xscale->jtag_info.ir_length = 5;
- }
- else if ((strcmp(xscale->variant, "pxa27x") == 0) ||
- (strcmp(xscale->variant, "ixp42x") == 0) ||
- (strcmp(xscale->variant, "ixp45x") == 0) ||
- (strcmp(xscale->variant, "ixp46x") == 0))
- {
- xscale->jtag_info.ir_length = 7;
+ if (ir_length && ir_length != tap->ir_length) {
+ LOG_WARNING("%s: IR length for %s is %d; fixing",
+ tap->dotted_name, variant, ir_length);
+ tap->ir_length = ir_length;
+ }
}
/* the debug handler isn't installed (and thus not running) at this time */
return ERROR_OK;
}
-/* target xscale <endianess> <startup_mode> <chain_pos> <variant> */
static int xscale_target_create(struct target_s *target, Jim_Interp *interp)
{
- xscale_common_t *xscale = calloc(1,sizeof(xscale_common_t));
+ xscale_common_t *xscale;
- xscale_init_arch_info(target, xscale, target->tap, target->variant);
- xscale_build_reg_cache(target);
+ if (xscale_debug_handler_size > 0x800) {
+ LOG_ERROR("debug_handler.bin: larger than 2kb");
+ return ERROR_FAIL;
+ }
- return ERROR_OK;
+ xscale = calloc(1, sizeof(*xscale));
+ if (!xscale)
+ return ERROR_FAIL;
+
+ return xscale_init_arch_info(target, xscale, target->tap,
+ target->variant);
}
static int
Code Review / openocd.git / blobdiff