jtag_add_pathmove(3, path);
else
{
- jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path);
+ jtag_add_pathmove(ARRAY_SIZE(noconsume_path), noconsume_path);
}
jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
static int xscale_arch_state(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
static const char *state[] =
{
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
arm_mode_name(armv4_5->core_mode),
- buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
+ buf_get_u32(armv4_5->cpsr->value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
state[xscale->armv4_5_mmu.mmu_enabled],
state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
static int xscale_debug_entry(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
uint32_t pc;
uint32_t buffer[10];
int i;
LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]);
}
- buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]);
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
+ arm_set_cpsr(armv4_5, buffer[9]);
LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
- armv4_5->core_mode = buffer[9] & 0x1f;
if (!is_arm_mode(armv4_5->core_mode))
{
target->state = TARGET_UNKNOWN;
LOG_DEBUG("target entered debug state in %s mode",
arm_mode_name(armv4_5->core_mode));
- if (buffer[9] & 0x20)
- armv4_5->core_state = ARMV4_5_STATE_THUMB;
- else
- armv4_5->core_state = ARMV4_5_STATE_ARM;
-
-
/* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
{
uint32_t address, int handle_breakpoints, int debug_execution)
{
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
struct breakpoint *breakpoint = target->breakpoints;
uint32_t current_pc;
int retval;
xscale_send_u32(target, 0x30);
/* send CPSR */
- xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
- LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+ xscale_send_u32(target,
+ buf_get_u32(armv4_5->cpsr->value, 0, 32));
+ LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
+ buf_get_u32(armv4_5->cpsr->value, 0, 32));
for (i = 7; i >= 0; i--)
{
xscale_send_u32(target, 0x30);
/* send CPSR */
- xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
- LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+ xscale_send_u32(target, buf_get_u32(armv4_5->cpsr->value, 0, 32));
+ LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
+ buf_get_u32(armv4_5->cpsr->value, 0, 32));
for (i = 7; i >= 0; i--)
{
if (!debug_execution)
{
/* registers are now invalid */
- armv4_5_invalidate_core_regs(target);
+ register_cache_invalidate(armv4_5->core_cache);
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
}
uint32_t address, int handle_breakpoints)
{
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
uint32_t next_pc;
int retval;
int i;
return retval;
/* send CPSR */
- if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK)
+ retval = xscale_send_u32(target,
+ buf_get_u32(armv4_5->cpsr->value, 0, 32));
+ if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+ LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
+ buf_get_u32(armv4_5->cpsr->value, 0, 32));
for (i = 7; i >= 0; i--)
{
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
/* registers are now invalid */
- if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
- return retval;
+ register_cache_invalidate(armv4_5->core_cache);
/* wait for and process debug entry */
if ((retval = xscale_debug_entry(target)) != ERROR_OK)
static int xscale_step(struct target *target, int current,
uint32_t address, int handle_breakpoints)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
struct breakpoint *breakpoint = target->breakpoints;
uint32_t current_pc;
breakpoint = breakpoint->next;
}
- armv4_5_invalidate_core_regs(target);
+ register_cache_invalidate(xscale->armv4_5_common.core_cache);
/* FIXME mark hardware watchpoints got unset too. Also,
* at least some of the XScale registers are invalid...
return ERROR_OK;
}
-static int xscale_read_core_reg(struct target *target, int num,
- enum armv4_5_mode mode)
+static int xscale_read_core_reg(struct target *target, struct reg *r,
+ int num, enum armv4_5_mode mode)
{
+ /** \todo add debug handler support for core register reads */
LOG_ERROR("not implemented");
return ERROR_OK;
}
-static int xscale_write_core_reg(struct target *target, int num,
- enum armv4_5_mode mode, uint32_t value)
+static int xscale_write_core_reg(struct target *target, struct reg *r,
+ int num, enum armv4_5_mode mode, uint32_t value)
{
+ /** \todo add debug handler support for core register writes */
LOG_ERROR("not implemented");
return ERROR_OK;
}
static int xscale_full_context(struct target *target)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
uint32_t *buffer;
static int xscale_restore_context(struct target *target)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
int i, j;
return ERROR_OK;
}
+static int xscale_read_phys_memory(struct target *target, uint32_t address,
+ uint32_t size, uint32_t count, uint8_t *buffer)
+{
+ /** \todo: provide a non-stub implementtion of this routine. */
+ LOG_ERROR("%s: %s is not implemented. Disable MMU?",
+ target_name(target), __func__);
+ return ERROR_FAIL;
+}
+
static int xscale_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
return ERROR_OK;
}
+static int xscale_write_phys_memory(struct target *target, uint32_t address,
+ uint32_t size, uint32_t count, uint8_t *buffer)
+{
+ /** \todo: provide a non-stub implementtion of this routine. */
+ LOG_ERROR("%s: %s is not implemented. Disable MMU?",
+ target_name(target), __func__);
+ return ERROR_FAIL;
+}
+
static int xscale_bulk_write_memory(struct target *target, uint32_t address,
uint32_t count, uint8_t *buffer)
{
{
struct xscale_common *xscale = target_to_xscale(target);
- if (target->state != TARGET_HALTED)
- {
- LOG_WARNING("target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
-
if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1))
{
LOG_INFO("no breakpoint unit available for hardware breakpoint");
{
struct xscale_common *xscale = target_to_xscale(target);
- if (target->state != TARGET_HALTED)
- {
- LOG_WARNING("target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
-
if (xscale->dbr_available < 1)
{
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
static int xscale_read_trace(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
struct xscale_trace_data **trace_data_p;
/* 258 words from debug handler
static void xscale_build_reg_cache(struct target *target)
{
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct xscale_reg *arch_info = malloc(sizeof(xscale_reg_arch_info));
int i;
- int num_regs = sizeof(xscale_reg_arch_info) / sizeof(struct xscale_reg);
+ int num_regs = ARRAY_SIZE(xscale_reg_arch_info);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
- armv4_5->core_cache = (*cache_p);
(*cache_p)->next = malloc(sizeof(struct reg_cache));
cache_p = &(*cache_p)->next;
if (CMD_ARGC >= 1)
{
- if (strcmp("enable", CMD_ARGV[0]) == 0)
- {
+ bool enable;
+ COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
+ if (enable)
xscale_enable_mmu_caches(target, 1, 0, 0);
- xscale->armv4_5_mmu.mmu_enabled = 1;
- }
- else if (strcmp("disable", CMD_ARGV[0]) == 0)
- {
+ else
xscale_disable_mmu_caches(target, 1, 0, 0);
- xscale->armv4_5_mmu.mmu_enabled = 0;
- }
+ xscale->armv4_5_mmu.mmu_enabled = enable;
}
command_print(CMD_CTX, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
{
struct target *target = get_current_target(CMD_CTX);
struct xscale_common *xscale = target_to_xscale(target);
- int icache = 0, dcache = 0;
- int retval;
- retval = xscale_verify_pointer(CMD_CTX, xscale);
+ int retval = xscale_verify_pointer(CMD_CTX, xscale);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
- if (strcmp(CMD_NAME, "icache") == 0)
- icache = 1;
- else if (strcmp(CMD_NAME, "dcache") == 0)
- dcache = 1;
+ bool icache;
+ COMMAND_PARSE_BOOL(CMD_NAME, icache, "icache", "dcache");
if (CMD_ARGC >= 1)
{
- if (strcmp("enable", CMD_ARGV[0]) == 0)
- {
- xscale_enable_mmu_caches(target, 0, dcache, icache);
-
- if (icache)
- xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 1;
- else if (dcache)
- xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 1;
- }
- else if (strcmp("disable", CMD_ARGV[0]) == 0)
- {
- xscale_disable_mmu_caches(target, 0, dcache, icache);
-
- if (icache)
- xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
- else if (dcache)
- xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
- }
+ bool enable;
+ COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
+ if (enable)
+ xscale_enable_mmu_caches(target, 1, 0, 0);
+ else
+ xscale_disable_mmu_caches(target, 1, 0, 0);
+ if (icache)
+ xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = enable;
+ else
+ xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = enable;
}
- if (icache)
- command_print(CMD_CTX, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled");
-
- if (dcache)
- command_print(CMD_CTX, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
+ bool enabled = icache ?
+ xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled :
+ xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled;
+ const char *msg = enabled ? "enabled" : "disabled";
+ command_print(CMD_CTX, "%s %s", CMD_NAME, msg);
return ERROR_OK;
}
{
struct target *target = get_current_target(CMD_CTX);
struct xscale_common *xscale = target_to_xscale(target);
- struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
+ struct arm *armv4_5 = &xscale->armv4_5_common;
uint32_t dcsr_value;
int retval;
return ERROR_OK;
}
-static int xscale_register_commands(struct command_context *cmd_ctx)
-{
- struct command *xscale_cmd;
-
- xscale_cmd = register_command(cmd_ctx, NULL, "xscale", NULL, COMMAND_ANY, "xscale specific commands");
-
- register_command(cmd_ctx, xscale_cmd, "debug_handler", xscale_handle_debug_handler_command, COMMAND_ANY, "'xscale debug_handler <target#> <address>' command takes two required operands");
- register_command(cmd_ctx, xscale_cmd, "cache_clean_address", xscale_handle_cache_clean_address_command, COMMAND_ANY, NULL);
-
- register_command(cmd_ctx, xscale_cmd, "cache_info", xscale_handle_cache_info_command, COMMAND_EXEC, NULL);
- register_command(cmd_ctx, xscale_cmd, "mmu", xscale_handle_mmu_command, COMMAND_EXEC, "['enable'|'disable'] the MMU");
- register_command(cmd_ctx, xscale_cmd, "icache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the ICache");
- register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache");
-
- register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_vector_catch_command, COMMAND_EXEC, "<mask> of vectors that should be catched");
- register_command(cmd_ctx, xscale_cmd, "vector_table", xscale_handle_vector_table_command, COMMAND_EXEC, "<high|low> <index> <code> set static code for exception handler entry");
-
- register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable | disable> ['fill' [n]|'wrap']");
-
- register_command(cmd_ctx, xscale_cmd, "dump_trace", xscale_handle_dump_trace_command, COMMAND_EXEC, "dump content of trace buffer to <file>");
- register_command(cmd_ctx, xscale_cmd, "analyze_trace", xscale_handle_analyze_trace_buffer_command, COMMAND_EXEC, "analyze content of trace buffer");
- register_command(cmd_ctx, xscale_cmd, "trace_image", xscale_handle_trace_image_command,
- COMMAND_EXEC, "load image from <file> [base address]");
-
- register_command(cmd_ctx, xscale_cmd, "cp15", xscale_handle_cp15, COMMAND_EXEC, "access coproc 15 <register> [value]");
-
- armv4_5_register_commands(cmd_ctx);
-
- return ERROR_OK;
-}
+static const struct command_registration xscale_exec_command_handlers[] = {
+ {
+ .name = "cache_info",
+ .handler = &xscale_handle_cache_info_command,
+ .mode = COMMAND_EXEC, NULL,
+ },
+
+ {
+ .name = "mmu",
+ .handler = &xscale_handle_mmu_command,
+ .mode = COMMAND_EXEC,
+ .usage = "[enable|disable]",
+ .help = "enable or disable the MMU",
+ },
+ {
+ .name = "icache",
+ .handler = &xscale_handle_idcache_command,
+ .mode = COMMAND_EXEC,
+ .usage = "[enable|disable]",
+ .help = "enable or disable the ICache",
+ },
+ {
+ .name = "dcache",
+ .handler = &xscale_handle_idcache_command,
+ .mode = COMMAND_EXEC,
+ .usage = "[enable|disable]",
+ .help = "enable or disable the DCache",
+ },
+
+ {
+ .name = "vector_catch",
+ .handler = &xscale_handle_vector_catch_command,
+ .mode = COMMAND_EXEC,
+ .help = "mask of vectors that should be caught",
+ .usage = "[<mask>]",
+ },
+ {
+ .name = "vector_table",
+ .handler = &xscale_handle_vector_table_command,
+ .mode = COMMAND_EXEC,
+ .usage = "<high|low> <index> <code>",
+ .help = "set static code for exception handler entry",
+ },
+
+ {
+ .name = "trace_buffer",
+ .handler = &xscale_handle_trace_buffer_command,
+ .mode = COMMAND_EXEC,
+ .usage = "<enable | disable> [fill [n]|wrap]",
+ },
+ {
+ .name = "dump_trace",
+ .handler = &xscale_handle_dump_trace_command,
+ .mode = COMMAND_EXEC,
+ .help = "dump content of trace buffer to <file>",
+ .usage = "<file>",
+ },
+ {
+ .name = "analyze_trace",
+ .handler = &xscale_handle_analyze_trace_buffer_command,
+ .mode = COMMAND_EXEC,
+ .help = "analyze content of trace buffer",
+ },
+ {
+ .name = "trace_image",
+ .handler = &xscale_handle_trace_image_command,
+ COMMAND_EXEC,
+ .help = "load image from <file> [base address]",
+ .usage = "<file> [address] [type]",
+ },
+
+ {
+ .name = "cp15",
+ .handler = &xscale_handle_cp15,
+ .mode = COMMAND_EXEC,
+ .help = "access coproc 15",
+ .usage = "<register> [value]",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration xscale_any_command_handlers[] = {
+ {
+ .name = "debug_handler",
+ .handler = &xscale_handle_debug_handler_command,
+ .mode = COMMAND_ANY,
+ .usage = "<target#> <address>",
+ },
+ {
+ .name = "cache_clean_address",
+ .handler = &xscale_handle_cache_clean_address_command,
+ .mode = COMMAND_ANY,
+ },
+ {
+ .chain = xscale_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration xscale_command_handlers[] = {
+ {
+ .chain = arm_command_handlers,
+ },
+ {
+ .name = "xscale",
+ .mode = COMMAND_ANY,
+ .help = "xscale command group",
+ .chain = xscale_any_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
struct target_type xscale_target =
{
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.read_memory = xscale_read_memory,
+ .read_phys_memory = xscale_read_phys_memory,
.write_memory = xscale_write_memory,
+ .write_phys_memory = xscale_write_phys_memory,
.bulk_write_memory = xscale_bulk_write_memory,
.checksum_memory = arm_checksum_memory,
.add_watchpoint = xscale_add_watchpoint,
.remove_watchpoint = xscale_remove_watchpoint,
- .register_commands = xscale_register_commands,
+ .commands = xscale_command_handlers,
.target_create = xscale_target_create,
.init_target = xscale_init_target,
Code Review / openocd.git / blobdiff