Cortex-M7: Give user a hint about single stepping problem up to r0p1.

[openocd.git] / src / target / x86_32_common.h

diff --git a/src/target/x86_32_common.h b/src/target/x86_32_common.h
index 83973b84a15cbdd2dfc747c3eef44f652e3a181f..c9cb389b52be59d517ec7d624afe6389b16aa5e0 100644 (file)
--- a/src/target/x86_32_common.h
+++ b/src/target/x86_32_common.h
@@ -1,5 +1,5 @@
 /*
- * Copyright(c) 2013 Intel Corporation.
+ * Copyright(c) 2013-2016 Intel Corporation.
  *
  * Adrian Burns (adrian.burns@intel.com)
  * Thomas Faust (thomas.faust@intel.com)
@@ -8,8 +8,9 @@
  * Jeffrey Maxwell (jeffrey.r.maxwell@intel.com)
  *
  * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful, but
  * WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -195,6 +196,11 @@ enum {
        WBINVD,
 };
 
+enum x86_core_type {
+       LMT1,
+       LMT3_5
+};
+
 struct swbp_mem_patch {
        uint8_t orig_byte;
        uint32_t swbp_unique_id;
@@ -208,6 +214,7 @@ struct swbp_mem_patch {
 struct x86_32_common {
        uint32_t common_magic;
        void *arch_info;
+       enum x86_core_type core_type;
        struct reg_cache *cache;
        struct jtag_tap *curr_tap;
        uint32_t stored_pc;