Duane Ellis: "target as an [tcl] object" feature.

[openocd.git] / src / target / target / str912.cfg

diff --git a/src/target/target/str912.cfg b/src/target/target/str912.cfg
index 14bb4973cad140ff184f0d7a54004aea0299e58d..2e0056a63a1b2855dbc4474190367ecb411b0bda 100644 (file)
--- a/src/target/target/str912.cfg
+++ b/src/target/target/str912.cfg
@@ -2,24 +2,7 @@
 
 # jtag speed. We need to stick to 16kHz until we've finished reset.
 
-jtag_khz 16
-proc target_0_pre_reset {} {
-       jtag_khz 16
-}
-
-proc target_0_post_reset {} {
-       # We can increase speed now that we know the target is halted.
-       jtag_khz 3000
-       
-       # -- Enable 96K RAM
-       # PFQBC enabled / DTCM & AHB wait-states disabled
-       mww 0x5C002034 0x0191 
-
-       str9x flash_config 0 4 2 0 0x80000
-       flash protect 0 0 7 off
-       
-       
-}
+jtag_rclk 16
 
 
 jtag_nsrst_delay 100
@@ -37,7 +20,21 @@ jtag_device 5 0x1 0x1 0x1e
 #target <type> <startup mode>
 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
 target arm966e little 1 arm966e
-run_and_halt_time 0 30
+
+[new_target_name] configure -event old-pre_reset { jtag_rclk 16 }
+
+[new_target_name] configure -event old-post_reset {
+       # We can increase speed now that we know the target is halted.
+       jtag_rclk 3000
+       
+       # -- Enable 96K RAM
+       # PFQBC enabled / DTCM & AHB wait-states disabled
+       mww 0x5C002034 0x0191 
+
+       str9x flash_config 0 4 2 0 0x80000
+       flash protect 0 0 7 off
+}
+
 
 
 working_area 0 0x50000000 16384 nobackup
@@ -47,4 +44,4 @@ flash bank str9x 0x00000000 0x00080000 0 0 0
 flash bank str9x 0x00080000 0x00008000 0 0 0
 
 # For more information about the configuration files, take a look at:
-# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger
+# openocd.texi