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coding style: open function's brace at beginning of new line
[openocd.git] / src / target / riscv / riscv.c
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 8b5a361bb8cd019d045f210f1a2553d07b239e39..afd0cc8152da08f05c6dbf693d03890430265330 100644 (file)
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -203,7 +203,7 @@ static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
 {
        struct scan_field field;
        uint8_t in_value[4];
-       uint8_t out_value[4];
+       uint8_t out_value[4] = { 0 };
 
        buf_set_u32(out_value, 0, 32, out);
 
@@ -540,7 +540,7 @@ int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
                        return ERROR_FAIL;
                }
 
-               uint8_t buff[4];
+               uint8_t buff[4] = { 0 };
                buf_set_u32(buff, 0, breakpoint->length * CHAR_BIT, breakpoint->length == 4 ? ebreak() : ebreak_c());
                int const retval = target_write_memory(target, breakpoint->address, 2, breakpoint->length / 2, buff);
 
@@ -772,12 +772,9 @@ static int oldriscv_step(struct target *target, int current, uint32_t address,
        return tt->step(target, current, address, handle_breakpoints);
 }
 
-static int old_or_new_riscv_step(
-               struct target *target,
-               int current,
-               target_addr_t address,
-               int handle_breakpoints
-){
+static int old_or_new_riscv_step(struct target *target, int current,
+               target_addr_t address, int handle_breakpoints)
+{
        RISCV_INFO(r);
        LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
        if (r->is_halted == NULL)
@@ -862,13 +859,9 @@ static int oldriscv_resume(struct target *target, int current, uint32_t address,
                        debug_execution);
 }
 
-static int old_or_new_riscv_resume(
-               struct target *target,
-               int current,
-               target_addr_t address,
-               int handle_breakpoints,
-               int debug_execution
-){
+static int old_or_new_riscv_resume(struct target *target, int current,
+               target_addr_t address, int handle_breakpoints, int debug_execution)
+{
        LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
        if (target->smp) {
                struct target_list *targets = target->head;
@@ -1047,7 +1040,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
 
        /* Disable Interrupts before attempting to run the algorithm. */
        uint64_t current_mstatus;
-       uint8_t mstatus_bytes[8];
+       uint8_t mstatus_bytes[8] = { 0 };
 
        LOG_DEBUG("Disabling Interrupts");
        struct reg *reg_mstatus = register_get_by_name(target->reg_cache,
@@ -1103,7 +1096,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
        reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
 
        /* Restore registers */
-       uint8_t buf[8];
+       uint8_t buf[8] = { 0 };
        buf_set_u64(buf, 0, info->xlen[0], saved_pc);
        if (reg_pc->type->set(reg_pc, buf) != ERROR_OK)
                return ERROR_FAIL;
@@ -1413,12 +1406,9 @@ int riscv_openocd_resume(
        return out;
 }
 
-int riscv_openocd_step(
-               struct target *target,
-               int current,
-               target_addr_t address,
-               int handle_breakpoints
-) {
+int riscv_openocd_step(struct target *target, int current,
+               target_addr_t address, int handle_breakpoints)
+{
        LOG_DEBUG("stepping rtos hart");
 
        if (!current)
@@ -1858,13 +1848,13 @@ static const struct command_registration riscv_exec_command_handlers[] = {
                .name = "test_sba_config_reg",
                .handler = riscv_test_sba_config_reg,
                .mode = COMMAND_ANY,
-               .usage = "riscv test_sba_config_reg legal_address num_words"
+               .usage = "riscv test_sba_config_reg legal_address num_words "
                        "illegal_address run_sbbusyerror_test[on/off]",
-               .help = "Perform a series of tests on the SBCS register."
-                       "Inputs are a legal, 128-byte aligned address and a number of words to"
-                       "read/write starting at that address (i.e., address range [legal address,"
-                       "legal_address+word_size*num_words) must be legally readable/writable)"
-                       ", an illegal, 128-byte aligned address for error flag/handling cases,"
+               .help = "Perform a series of tests on the SBCS register. "
+                       "Inputs are a legal, 128-byte aligned address and a number of words to "
+                       "read/write starting at that address (i.e., address range [legal address, "
+                       "legal_address+word_size*num_words) must be legally readable/writable), "
+                       "an illegal, 128-byte aligned address for error flag/handling cases, "
                        "and whether sbbusyerror test should be run."
        },
        {
@@ -1887,11 +1877,6 @@ static const struct command_registration riscv_exec_command_handlers[] = {
        COMMAND_REGISTRATION_DONE
 };
 
-extern __COMMAND_HANDLER(handle_common_semihosting_command);
-extern __COMMAND_HANDLER(handle_common_semihosting_fileio_command);
-extern __COMMAND_HANDLER(handle_common_semihosting_resumable_exit_command);
-extern __COMMAND_HANDLER(handle_common_semihosting_cmdline);
-
 /*
  * To be noted that RISC-V targets use the same semihosting commands as
  * ARM targets.
@@ -1905,37 +1890,7 @@ extern __COMMAND_HANDLER(handle_common_semihosting_cmdline);
  * protocol, then a command like `riscv semihosting enable` will make
  * sense, but for now all semihosting commands are prefixed with `arm`.
  */
-static const struct command_registration arm_exec_command_handlers[] = {
-       {
-               .name = "semihosting",
-               .handler = handle_common_semihosting_command,
-               .mode = COMMAND_EXEC,
-               .usage = "['enable'|'disable']",
-               .help = "activate support for semihosting operations",
-       },
-       {
-               .name = "semihosting_cmdline",
-               .handler = handle_common_semihosting_cmdline,
-               .mode = COMMAND_EXEC,
-               .usage = "arguments",
-               .help = "command line arguments to be passed to program",
-       },
-       {
-               .name = "semihosting_fileio",
-               .handler = handle_common_semihosting_fileio_command,
-               .mode = COMMAND_EXEC,
-               .usage = "['enable'|'disable']",
-               .help = "activate support for semihosting fileio operations",
-       },
-       {
-               .name = "semihosting_resexit",
-               .handler = handle_common_semihosting_resumable_exit_command,
-               .mode = COMMAND_EXEC,
-               .usage = "['enable'|'disable']",
-               .help = "activate support for semihosting resumable exit",
-       },
-       COMMAND_REGISTRATION_DONE
-};
+extern const struct command_registration semihosting_common_handlers[];
 
 const struct command_registration riscv_command_handlers[] = {
        {
@@ -1950,7 +1905,7 @@ const struct command_registration riscv_command_handlers[] = {
                .mode = COMMAND_ANY,
                .help = "ARM Command Group",
                .usage = "",
-               .chain = arm_exec_command_handlers
+               .chain = semihosting_common_handlers
        },
        COMMAND_REGISTRATION_DONE
 };
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