hla: Make consistent parameter naming

[openocd.git] / src / target / nds32_v2.c

diff --git a/src/target/nds32_v2.c b/src/target/nds32_v2.c
index 3f5f636fd79a9b3cc205186ac1c79f000231c057..24f5108ccb2d2b07dedfbd6374985efb8a9726c2 100644 (file)
--- a/src/target/nds32_v2.c
+++ b/src/target/nds32_v2.c
@@ -245,7 +245,6 @@ static int nds32_v2_check_interrupt_stack(struct nds32_v2_common *nds32_v2)
                return ERROR_OK;
        }
 
-
        /* There is a case that single step also trigger another interrupt,
           then HSS bit in psw(ir0) will push to ipsw(ir1).
           Then hit debug interrupt HSS bit in ipsw(ir1) will push to (p_ipsw)ir2
@@ -288,21 +287,12 @@ static int nds32_v2_debug_entry(struct nds32 *nds32, bool enable_watchpoint)
 {
        LOG_DEBUG("nds32_v2_debug_entry");
 
-       jtag_poll_set_enabled(false);
-
        if (nds32->virtual_hosting)
                LOG_WARNING("<-- TARGET WARNING! Virtual hosting is not supported "
                                "under V1/V2 architecture. -->");
 
-       struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(nds32->target);
-
-       CHECK_RETVAL(nds32_v2_deactivate_hardware_breakpoint(nds32->target));
-
-       if (enable_watchpoint)
-               CHECK_RETVAL(nds32_v2_deactivate_hardware_watchpoint(nds32->target));
-
+       enum target_state backup_state = nds32->target->state;
        nds32->target->state = TARGET_HALTED;
-       nds32_examine_debug_reason(nds32);
 
        if (nds32->init_arch_info_after_halted == false) {
                /* init architecture info according to config registers */
@@ -314,8 +304,30 @@ static int nds32_v2_debug_entry(struct nds32 *nds32, bool enable_watchpoint)
        /* REVISIT entire cache should already be invalid !!! */
        register_cache_invalidate(nds32->core_cache);
 
+       /* deactivate all hardware breakpoints */
+       CHECK_RETVAL(nds32_v2_deactivate_hardware_breakpoint(nds32->target));
+
+       if (enable_watchpoint)
+               CHECK_RETVAL(nds32_v2_deactivate_hardware_watchpoint(nds32->target));
+
+       if (ERROR_OK != nds32_examine_debug_reason(nds32)) {
+               nds32->target->state = backup_state;
+
+               /* re-activate all hardware breakpoints & watchpoints */
+               CHECK_RETVAL(nds32_v2_activate_hardware_breakpoint(nds32->target));
+
+               if (enable_watchpoint) {
+                       /* activate all watchpoints */
+                       CHECK_RETVAL(nds32_v2_activate_hardware_watchpoint(nds32->target));
+               }
+
+               return ERROR_FAIL;
+       }
+
        /* check interrupt level before .full_context(), because
-        * get_mapped_reg needs current_interrupt_level information */
+        * get_mapped_reg() in nds32_full_context() needs current_interrupt_level
+        * information */
+       struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(nds32->target);
        nds32_v2_check_interrupt_stack(nds32_v2);
 
        /* Save registers. */
@@ -350,7 +362,9 @@ static int nds32_v2_target_request_data(struct target *target,
  */
 static int nds32_v2_leave_debug_state(struct nds32 *nds32, bool enable_watchpoint)
 {
-       struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(nds32->target);
+       LOG_DEBUG("nds32_v2_leave_debug_state");
+
+       struct target *target = nds32->target;
 
        /* activate all hardware breakpoints */
        CHECK_RETVAL(nds32_v2_activate_hardware_breakpoint(nds32->target));
@@ -361,38 +375,16 @@ static int nds32_v2_leave_debug_state(struct nds32 *nds32, bool enable_watchpoin
        }
 
        /* restore interrupt stack */
+       struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(nds32->target);
        nds32_v2_restore_interrupt_stack(nds32_v2);
 
        /* restore PSW, PC, and R0 ... after flushing any modified
         * registers.
         */
-       CHECK_RETVAL(nds32_restore_context(nds32->target));
+       CHECK_RETVAL(nds32_restore_context(target));
 
        register_cache_invalidate(nds32->core_cache);
 
-       jtag_poll_set_enabled(true);
-
-       return ERROR_OK;
-}
-
-static int nds32_v2_soft_reset_halt(struct target *target)
-{
-       /* TODO: test it */
-       struct nds32 *nds32 = target_to_nds32(target);
-       struct aice_port_s *aice = target_to_aice(target);
-
-       aice_assert_srst(aice, AICE_SRST);
-
-       /* halt core and set pc to 0x0 */
-       int retval = target_halt(target);
-       if (retval != ERROR_OK)
-               return retval;
-
-       /* start fetching from IVB */
-       uint32_t value_ir3;
-       nds32_get_mapped_reg(nds32, IR3, &value_ir3);
-       nds32_set_mapped_reg(nds32, PC, value_ir3 & 0xFFFF0000);
-
        return ERROR_OK;
 }
 
@@ -409,10 +401,6 @@ static int nds32_v2_deassert_reset(struct target *target)
                retval = target_halt(target);
                if (retval != ERROR_OK)
                        return retval;
-               /* call target_poll() to avoid "Halt timed out" */
-               CHECK_RETVAL(target_poll(target));
-       } else {
-               jtag_poll_set_enabled(false);
        }
 
        return ERROR_OK;
@@ -765,7 +753,6 @@ struct target_type nds32_v2_target = {
 
        .assert_reset = nds32_assert_reset,
        .deassert_reset = nds32_v2_deassert_reset,
-       .soft_reset_halt = nds32_v2_soft_reset_halt,
 
        /* register access */
        .get_gdb_reg_list = nds32_get_gdb_reg_list,