mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ /* clear this bit before handling polling
+ * as after reset registers will read zero */
+ if (ejtag_ctrl & EJTAG_CTRL_ROCC)
+ {
+ /* we have detected a reset, clear flag
+ * otherwise ejtag will not work */
+ jtag_add_end_state(TAP_RTI);
+ ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
+
+ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+ mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+ LOG_DEBUG("Reset Detected");
+ }
+
+ /* check for processor halted */
if (ejtag_ctrl & EJTAG_CTRL_BRKST)
{
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
target->state = TARGET_RUNNING;
}
- if (ejtag_ctrl & EJTAG_CTRL_ROCC)
- {
- /* we have detected a reset, clear flag
- * otherwise ejtag will not work */
- jtag_add_end_state(TAP_RTI);
- ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
-
- mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
- mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
- LOG_DEBUG("Reset Detected");
- }
-
// LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
return ERROR_OK;
{
mips32_common_t *mips32 = target->arch_info;
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
+ mips_m4k_common_t *mips_m4k = mips32->arch_info;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
+ Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
if (!(jtag_reset_config & RESET_HAS_SRST))
{
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
}
- if (strcmp(target->variant, "ejtag_srst") == 0) {
+ if (strcmp(mips_m4k->variant, "ejtag_srst") == 0)
+ {
u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
- } else {
+ }
+ else
+ {
/* here we should issue a srst only, but we may have to assert trst as well */
if (jtag_reset_config & RESET_SRST_PULLS_TRST)
{
mips32_invalidate_core_regs(target);
- if (target->reset_halt)
- {
- int retval;
+ if (target->reset_halt)
+ {
+ int retval;
if ((retval = target_halt(target))!=ERROR_OK)
return retval;
- }
-
+ }
return ERROR_OK;
}
int mips_m4k_deassert_reset(target_t *target)
{
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
+ Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
/* deassert reset lines */
jtag_add_reset(0, 0);
}
/* current = 1: continue on current pc, otherwise continue at <address> */
- if (!current)
+ if (!current)
{
buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
case 2:
case 1:
/* if noDMA off, use DMAACC mode for memory read */
- if(ejtag_info->impcode & (1<<14))
+ if(ejtag_info->impcode & EJTAG_IMP_NODMA)
return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
else
return mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
case 2:
case 1:
/* if noDMA off, use DMAACC mode for memory write */
- if(ejtag_info->impcode & (1<<14))
+ if(ejtag_info->impcode & EJTAG_IMP_NODMA)
mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
else
mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
/* initialize mips4k specific info */
mips32_init_arch_info(target, mips32, chain_pos, variant);
mips32->arch_info = mips_m4k;
-
+
return ERROR_OK;
}