target/riscv-011: Fix memory leak in handle_halt_routine()

[openocd.git] / src / target / mips_m4k.c

diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index e2007d99efdc58d400698d8a780daef9cb4cbd2c..20c707bb62afc9e1b506afa9f0a6243c8dbea1fa 100644 (file)
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -344,6 +344,8 @@ static int mips_m4k_assert_reset(struct target *target)
                        jtag_add_reset(1, 1);
                else if (!srst_asserted)
                        jtag_add_reset(0, 1);
+       } else if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
+               target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
        } else {
                if (mips_m4k->is_pic32mx) {
                        LOG_DEBUG("Using MTAP reset to reset processor...");
@@ -702,7 +704,7 @@ static int mips_m4k_set_breakpoint(struct target *target,
                        }
 
                        if (verify == 0) {
-                               LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx64
+                               LOG_ERROR("Unable to set 32bit breakpoint at address %08" TARGET_PRIxADDR
                                        " - check that memory is read/writable", breakpoint->address);
                                return ERROR_OK;
                        }
@@ -723,7 +725,7 @@ static int mips_m4k_set_breakpoint(struct target *target,
                                return retval;
 
                        if (verify != MIPS16_SDBBP(isa_req)) {
-                               LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx64
+                               LOG_ERROR("Unable to set 16bit breakpoint at address %08" TARGET_PRIxADDR
                                                " - check that memory is read/writable", breakpoint->address);
                                return ERROR_OK;
                        }
@@ -1174,36 +1176,30 @@ static int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
 
 static int mips_m4k_examine(struct target *target)
 {
-       int retval;
        struct mips_m4k_common *mips_m4k = target_to_m4k(target);
        struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
-       uint32_t idcode = 0;
 
        if (!target_was_examined(target)) {
-               retval = mips_ejtag_get_idcode(ejtag_info, &idcode);
-               if (retval != ERROR_OK)
+               int retval = mips_ejtag_get_idcode(ejtag_info);
+               if (retval != ERROR_OK) {
+                       LOG_ERROR("idcode read failed");
                        return retval;
-               ejtag_info->idcode = idcode;
-
-               if (((idcode >> 1) & 0x7FF) == 0x29) {
+               }
+               if (((ejtag_info->idcode >> 1) & 0x7FF) == 0x29) {
                        /* we are using a pic32mx so select ejtag port
                         * as it is not selected by default */
                        mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
-                       LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
+                       LOG_DEBUG("PIC32 Detected - using EJTAG Interface");
                        mips_m4k->is_pic32mx = true;
                }
        }
 
        /* init rest of ejtag interface */
-       retval = mips_ejtag_init(ejtag_info);
+       int retval = mips_ejtag_init(ejtag_info);
        if (retval != ERROR_OK)
                return retval;
 
-       retval = mips32_examine(target);
-       if (retval != ERROR_OK)
-               return retval;
-
-       return ERROR_OK;
+       return mips32_examine(target);
 }
 
 static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t address,