/* check for processor halted */
if (ejtag_ctrl & EJTAG_CTRL_BRKST) {
+ if (target->state == TARGET_UNKNOWN) {
+ LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
+
+ /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
+ * (maybe put on by HALT-ing the board in the previous session).
+ *
+ * Force target to RUNNING state to enable debug entry for this session.
+ */
+ target->state = TARGET_RUNNING;
+ }
+
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) {
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
return ERROR_TARGET_FAILURE;
} else {
/* we came here in a reset_halt or reset_init sequence
- * debug entry was already prepared in mips32_prepare_reset_halt()
+ * debug entry was already prepared in mips_m4k_assert_reset()
*/
target->debug_reason = DBG_REASON_DBGRQ;
{
struct mips_m4k_common *mips_m4k = target_to_m4k(target);
struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
- int assert_srst = 1;
LOG_DEBUG("target->state: %s",
target_state_name(target));
enum reset_types jtag_reset_config = jtag_get_reset_config();
- if (!(jtag_reset_config & RESET_HAS_SRST))
- assert_srst = 0;
+ /* some cores support connecting while srst is asserted
+ * use that mode is it has been configured */
+
+ bool srst_asserted = false;
+
+ if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
+ (jtag_reset_config & RESET_SRST_NO_GATING)) {
+ jtag_add_reset(0, 1);
+ srst_asserted = true;
+ }
if (target->reset_halt) {
/* use hardware to catch reset */
} else
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
- if (assert_srst) {
+ if (jtag_reset_config & RESET_HAS_SRST) {
/* here we should issue a srst only, but we may have to assert trst as well */
if (jtag_reset_config & RESET_SRST_PULLS_TRST)
jtag_add_reset(1, 1);
- else
+ else if (!srst_asserted)
jtag_add_reset(0, 1);
} else {
if (mips_m4k->is_pic32mx) {