Convert to non-recursive make

[openocd.git] / src / target / mips_ejtag.h

diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h
index db20e9d0dfdf31f3f80eb24d19b542d35d6c2a13..6ef08675da70ad7bc884cb56e095fd1e274804c0 100644 (file)
--- a/src/target/mips_ejtag.h
+++ b/src/target/mips_ejtag.h
@@ -15,13 +15,11 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
-#ifndef MIPS_EJTAG
-#define MIPS_EJTAG
+#ifndef OPENOCD_TARGET_MIPS_EJTAG_H
+#define OPENOCD_TARGET_MIPS_EJTAG_H
 
 #include <jtag/jtag.h>
 
@@ -97,11 +95,35 @@
 #define EJTAG_DEBUG_DM                 (1 << 30)
 #define EJTAG_DEBUG_DBD                        (1 << 31)
 
-/* implementaion register bits */
-#define EJTAG_IMP_R3K                  (1 << 28)
-#define EJTAG_IMP_DINT                 (1 << 24)
-#define EJTAG_IMP_NODMA                        (1 << 14)
+/* implementation MIPS register bits.
+ * Bits marked with V20 or v2.0 mean that, this registers supported only
+ * by EJTAG v2.0. Bits marked with Lexra or BMIPS are different from the
+ * official EJATG.
+ * NOTE: Lexra or BMIPS use EJTAG v2.0 */
+
+#define EJTAG_IMP_HAS(x)                       (ejtag_info->impcode & (x))
+/* v2.0(Lexra) 29 - 1’b1 - Lexra Internal Trace Buffer implemented. This bit
+ * overlaps with version bit of MIPS EJTAG specification. */
+#define EJTAG_V26_IMP_R3K              (1 << 28)
+/* v2.0 - 24:25 - 2’b00- No profiling support */
+#define EJTAG_V26_IMP_DINT             (1 << 24)
+#define EJTAG_V20_IMP_SDBBP            (1 << 23) /* 1’b1 - sdbbp is Special2 Opcode */
+#define EJTAG_IMP_ASID8                        (1 << 22)
+#define EJTAG_IMP_ASID6                        (1 << 21)
+#define EJTAG_V20_IMP_COMPLEX_BREAK    (1 << 20) /* Complex Breaks supported*/
+#define EJTAG_V20_IMP_EADDR_NO32BIT    (1 << 19) /* EJTAG_ADDR > 32 bits wide */
+#define EJTAG_V20_IMP_DCACHE_COH       (1 << 18) /* DCache does keep DMA coherent */
+#define EJTAG_V20_IMP_ICACHE_COH       (1 << 17) /* DCache does keep DMA coherent */
 #define EJTAG_IMP_MIPS16               (1 << 16)
+#define EJTAG_IMP_NODMA                        (1 << 14)
+/* v2.0 - 11:13 external PC trace. Trace PC Width. */
+/* v2.0 - 8:10 external PC trace. PCST Width and DCLK Division Factor */
+#define EJTAG_V20_IMP_NOPB             (1 << 7) /* no processor breaks */
+#define EJTAG_V20_IMP_NODB             (1 << 6) /* no data breaks */
+#define EJTAG_V20_IMP_NOIB             (1 << 5) /* no instruction breaks implemented */
+/* v2.0 - 1:4 Number of Break Channels. */
+#define EJTAG_V20_IMP_BCHANNELS_MASK   0xf
+#define EJTAG_V20_IMP_BCHANNELS_SHIFT  1
 #define EJTAG_DCR_MIPS64               (1 << 0)
 
 /* Debug Control Register DCR */
@@ -120,7 +142,7 @@
 #define EJTAG_V20_IBC_OFFS             0x4     /* IBC Offset */
 #define EJTAG_V20_IBM_OFFS             0x8
 #define EJTAG_V20_IBAn_STEP            0x10    /* Offset for next channel */
-#define EJTAG_V20_DBS                  0xFF30008
+#define EJTAG_V20_DBS                  0xFF300008
 #define EJTAG_V20_DBA0                 0xFF300200
 #define EJTAG_V20_DBC_OFFS             0x4
 #define EJTAG_V20_DBM_OFFS             0x8
@@ -164,10 +186,13 @@ struct mips_ejtag {
        uint32_t reg9;
        unsigned scan_delay;
        int mode;
+       uint32_t pa_ctrl;
+       uint32_t pa_addr;
        unsigned int ejtag_version;
 
        /* Memory-Mapped Registers. This addresses are not same on different
         * EJTAG versions. */
+       uint32_t debug_caps;
        uint32_t ejtag_ibs_addr;        /* Instruction Address Break Status */
        uint32_t ejtag_iba0_addr;       /* IAB channel 0 */
        uint32_t ejtag_ibc_offs;        /* IAB Control offset */
@@ -182,8 +207,7 @@ struct mips_ejtag {
        uint32_t ejtag_dbasid_offs;     /* DAB ASID (4Kc) */
 
        uint32_t ejtag_iba_step_size;
-       uint32_t ejtag_dba_step_size;   /* siez of step till next
-                                        * *DBAn register. */
+       uint32_t ejtag_dba_step_size;   /* size of step till next *DBAn register. */
 };
 
 void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info,
@@ -208,4 +232,4 @@ static inline void mips_le_to_h_u32(jtag_callback_data_t arg)
        *((uint32_t *)arg) = le_to_h_u32(in);
 }
 
-#endif /* MIPS_EJTAG */
+#endif /* OPENOCD_TARGET_MIPS_EJTAG_H */