Code Review / openocd.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | inline | side by side
target_timer_callback_t -> struct target_timer_callback
[openocd.git] / src / target / mips32_dmaacc.c
diff --git a/src/target/mips32_dmaacc.c b/src/target/mips32_dmaacc.c
index 7ca6c29add48d2f845d23a4f98b05c76b1414878..aa36d2cf6e05ad653d97e770f0b19d142090f33b 100644 (file)
--- a/src/target/mips32_dmaacc.c
+++ b/src/target/mips32_dmaacc.c
@@ -26,11 +26,9 @@
 #include "config.h"
 #endif
 
-#include <string.h>
-#include "log.h"
-#include "mips32.h"
 #include "mips32_dmaacc.h"
 
+
 /*
  * The following logic shamelessly cloned from HairyDairyMaid's wrt54g_debrick
  * to support the Broadcom BCM5352 SoC in the Linksys WRT54GL wireless router
@@ -41,398 +39,418 @@
  * displaying/modifying memory and memory mapped registers.
  */
 
-static int ejtag_dma_read(mips_ejtag_t *ejtag_info, u32 addr, u32 *data)
+static int ejtag_dma_read(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *data)
 {
-       u32 v;
-       u32 ctrl_reg;
-       int   retries = RETRY_ATTEMPTS;
+       uint32_t v;
+       uint32_t ejtag_ctrl;
+       int retries = RETRY_ATTEMPTS;
 
 begin_ejtag_dma_read:
 
-       // Setup Address
+       /* Setup Address */
        v = addr;
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
        mips_ejtag_drscan_32(ejtag_info, &v);
 
-       // Initiate DMA Read & set DSTRT
+       /* Initiate DMA Read & set DSTRT */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+       ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
-       // Wait for DSTRT to Clear
+       /* Wait for DSTRT to Clear */
        do {
-               ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-               mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+               ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
-       // Read Data
+       /* Read Data */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
        mips_ejtag_drscan_32(ejtag_info, data);
 
-       // Clear DMA & Check DERR
+       /* Clear DMA & Check DERR */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       if (ctrl_reg  & EJTAG_CTRL_DERR)
+       ejtag_ctrl = ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       if (ejtag_ctrl  & EJTAG_CTRL_DERR)
        {
                if (retries--) {
-                       printf("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);
+                       LOG_ERROR("DMA Read Addr = %08" PRIx32 "  Data = ERROR ON READ (retrying)\n", addr);
                        goto begin_ejtag_dma_read;
-               } else  printf("DMA Read Addr = %08x  Data = ERROR ON READ\n", addr);
+               }
+               else
+                       LOG_ERROR("DMA Read Addr = %08" PRIx32 "  Data = ERROR ON READ\n", addr);
                return ERROR_JTAG_DEVICE_ERROR;
        }
 
        return ERROR_OK;
 }
 
-static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, u16 *data)
+static int ejtag_dma_read_h(struct mips_ejtag *ejtag_info, uint32_t addr, uint16_t *data)
 {
-       u32 v;
-       u32 ctrl_reg;
-       int   retries = RETRY_ATTEMPTS;
+       uint32_t v;
+       uint32_t ejtag_ctrl;
+       int retries = RETRY_ATTEMPTS;
 
 begin_ejtag_dma_read_h:
 
-       // Setup Address
+       /* Setup Address */
        v = addr;
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
        mips_ejtag_drscan_32(ejtag_info, &v);
 
-       // Initiate DMA Read & set DSTRT
+       /* Initiate DMA Read & set DSTRT */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+       ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
-       // Wait for DSTRT to Clear
+       /* Wait for DSTRT to Clear */
        do {
-               ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-               mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+               ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
-       // Read Data
+       /* Read Data */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
        mips_ejtag_drscan_32(ejtag_info, &v);
 
-       // Clear DMA & Check DERR
+       /* Clear DMA & Check DERR */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       if (ctrl_reg  & EJTAG_CTRL_DERR)
+       ejtag_ctrl = ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       if (ejtag_ctrl  & EJTAG_CTRL_DERR)
        {
                if (retries--) {
-                       printf("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);
+                       LOG_ERROR("DMA Read Addr = %08" PRIx32 "  Data = ERROR ON READ (retrying)\n", addr);
                        goto begin_ejtag_dma_read_h;
-               } else  printf("DMA Read Addr = %08x  Data = ERROR ON READ\n", addr);
+               }
+               else
+                       LOG_ERROR("DMA Read Addr = %08" PRIx32 "  Data = ERROR ON READ\n", addr);
                return ERROR_JTAG_DEVICE_ERROR;
        }
 
-       // Handle the bigendian/littleendian
-       if ( addr & 0x2 )  *data = (v>>16)&0xffff ;
-       else               *data = (v&0x0000ffff) ;
+       /* Handle the bigendian/littleendian */
+       if (addr & 0x2)
+               *data = (v >> 16) & 0xffff;
+       else
+               *data = (v & 0x0000ffff);
 
        return ERROR_OK;
 }
 
-static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, u32 addr, u8 *data)
+static int ejtag_dma_read_b(struct mips_ejtag *ejtag_info, uint32_t addr, uint8_t *data)
 {
-       u32 v;
-       u32 ctrl_reg;
-       int   retries = RETRY_ATTEMPTS;
+       uint32_t v;
+       uint32_t ejtag_ctrl;
+       int retries = RETRY_ATTEMPTS;
 
 begin_ejtag_dma_read_b:
 
-       // Setup Address
+       /* Setup Address */
        v = addr;
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
        mips_ejtag_drscan_32(ejtag_info, &v);
 
-       // Initiate DMA Read & set DSTRT
+       /* Initiate DMA Read & set DSTRT */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+       ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
-       // Wait for DSTRT to Clear
+       /* Wait for DSTRT to Clear */
        do {
-               ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-               mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+               ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
-       // Read Data
+       /* Read Data */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
        mips_ejtag_drscan_32(ejtag_info, &v);
 
-       // Clear DMA & Check DERR
+       /* Clear DMA & Check DERR */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       if (ctrl_reg  & EJTAG_CTRL_DERR)
+       ejtag_ctrl = ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       if (ejtag_ctrl  & EJTAG_CTRL_DERR)
        {
                if (retries--) {
-                       printf("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);
+                       LOG_ERROR("DMA Read Addr = %08" PRIx32 "  Data = ERROR ON READ (retrying)\n", addr);
                        goto begin_ejtag_dma_read_b;
-               } else  printf("DMA Read Addr = %08x  Data = ERROR ON READ\n", addr);
+               }
+               else
+                       LOG_ERROR("DMA Read Addr = %08" PRIx32 "  Data = ERROR ON READ\n", addr);
                return ERROR_JTAG_DEVICE_ERROR;
        }
 
-       // Handle the bigendian/littleendian
-       switch(addr & 0x3) {
-       case 0:  *data =  v      & 0xff; break;
-       case 1:  *data = (v>>8)  & 0xff; break;
-       case 2:  *data = (v>>16) & 0xff; break;
-       case 3:  *data = (v>>24) & 0xff; break;
+       /* Handle the bigendian/littleendian */
+       switch (addr & 0x3) {
+               case 0:
+                       *data = v & 0xff;
+                       break;
+               case 1:
+                       *data = (v >> 8) & 0xff;
+                       break;
+               case 2:
+                       *data = (v >> 16) & 0xff;
+                       break;
+               case 3:
+                       *data = (v >> 24) & 0xff;
+                       break;
        }
 
        return ERROR_OK;
 }
 
-static int ejtag_dma_write(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
+static int ejtag_dma_write(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data)
 {
-       u32 v;
-       u32 ctrl_reg;
-       int   retries = RETRY_ATTEMPTS;
+       uint32_t v;
+       uint32_t ejtag_ctrl;
+       int retries = RETRY_ATTEMPTS;
 
 begin_ejtag_dma_write:
 
-       // Setup Address
+       /* Setup Address */
        v = addr;
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
        mips_ejtag_drscan_32(ejtag_info, &v);
 
-       // Setup Data
+       /* Setup Data */
        v = data;
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
        mips_ejtag_drscan_32(ejtag_info, &v);
 
-       // Initiate DMA Write & set DSTRT
+       /* Initiate DMA Write & set DSTRT */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+       ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
-       // Wait for DSTRT to Clear
+       /* Wait for DSTRT to Clear */
        do {
-               ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-               mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+               ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
-       // Clear DMA & Check DERR
+       /* Clear DMA & Check DERR */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       if (ctrl_reg  & EJTAG_CTRL_DERR)
+       ejtag_ctrl = ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       if (ejtag_ctrl  & EJTAG_CTRL_DERR)
        {
                if (retries--) {
-                       printf("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);
+                       LOG_ERROR("DMA Write Addr = %08" PRIx32 "  Data = ERROR ON WRITE (retrying)\n", addr);
                        goto begin_ejtag_dma_write;
-               } else  printf("DMA Write Addr = %08x  Data = ERROR ON WRITE\n", addr);
+               }
+               else
+                       LOG_ERROR("DMA Write Addr = %08" PRIx32 "  Data = ERROR ON WRITE\n", addr);
                return ERROR_JTAG_DEVICE_ERROR;
        }
 
        return ERROR_OK;
 }
 
-static int ejtag_dma_write_h(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
+static int ejtag_dma_write_h(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data)
 {
-       u32 v;
-       u32 ctrl_reg;
-       int   retries = RETRY_ATTEMPTS;
+       uint32_t v;
+       uint32_t ejtag_ctrl;
+       int retries = RETRY_ATTEMPTS;
 
-
-       // Handle the bigendian/littleendian
+       /* Handle the bigendian/littleendian */
        data &= 0xffff;
-       data |= data<<16;
+       data |= data << 16;
 
 begin_ejtag_dma_write_h:
 
-       // Setup Address
+       /* Setup Address */
        v = addr;
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
        mips_ejtag_drscan_32(ejtag_info, &v);
 
-       // Setup Data
+       /* Setup Data */
        v = data;
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
        mips_ejtag_drscan_32(ejtag_info, &v);
 
-       // Initiate DMA Write & set DSTRT
+       /* Initiate DMA Write & set DSTRT */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+       ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
-       // Wait for DSTRT to Clear
+       /* Wait for DSTRT to Clear */
        do {
-               ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-               mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+               ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
-       // Clear DMA & Check DERR
+       /* Clear DMA & Check DERR */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       if (ctrl_reg  & EJTAG_CTRL_DERR)
+       ejtag_ctrl = ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       if (ejtag_ctrl  & EJTAG_CTRL_DERR)
        {
                if (retries--) {
-                       printf("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);
+                       LOG_ERROR("DMA Write Addr = %08" PRIx32 "  Data = ERROR ON WRITE (retrying)\n", addr);
                        goto begin_ejtag_dma_write_h;
-               } else  printf("DMA Write Addr = %08x  Data = ERROR ON WRITE\n", addr);
+               }
+               else
+                       LOG_ERROR("DMA Write Addr = %08" PRIx32 "  Data = ERROR ON WRITE\n", addr);
                return ERROR_JTAG_DEVICE_ERROR;
        }
 
        return ERROR_OK;
 }
 
-static int ejtag_dma_write_b(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
+static int ejtag_dma_write_b(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data)
 {
-       u32 v;
-       u32 ctrl_reg;
-       int   retries = RETRY_ATTEMPTS;
-
+       uint32_t v;
+       uint32_t ejtag_ctrl;
+       int retries = RETRY_ATTEMPTS;
 
-       // Handle the bigendian/littleendian
+       /* Handle the bigendian/littleendian */
        data &= 0xff;
-       data |= data<<8;
-       data |= data<<16;
+       data |= data << 8;
+       data |= data << 16;
 
 begin_ejtag_dma_write_b:
 
-       // Setup Address
+       /*  Setup Address*/
        v = addr;
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
        mips_ejtag_drscan_32(ejtag_info, &v);
 
-       // Setup Data
+       /* Setup Data */
        v = data;
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
        mips_ejtag_drscan_32(ejtag_info, &v);
 
-       // Initiate DMA Write & set DSTRT
+       /* Initiate DMA Write & set DSTRT */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
+       ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
-       // Wait for DSTRT to Clear
+       /* Wait for DSTRT to Clear */
        do {
-               ctrl_reg = EJTAG_CTRL_DMAACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-               mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       } while(ctrl_reg & EJTAG_CTRL_DSTRT);
+               ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
+               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
-       // Clear DMA & Check DERR
+       /* Clear DMA & Check DERR */
        mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-       ctrl_reg = EJTAG_CTRL_PROBEN | EJTAG_CTRL_PRACC;
-       mips_ejtag_drscan_32(ejtag_info, &ctrl_reg);
-       if (ctrl_reg  & EJTAG_CTRL_DERR)
+       ejtag_ctrl = ejtag_info->ejtag_ctrl;
+       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       if (ejtag_ctrl & EJTAG_CTRL_DERR)
        {
                if (retries--) {
-                       printf("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);
+                       LOG_ERROR("DMA Write Addr = %08" PRIx32 "  Data = ERROR ON WRITE (retrying)\n", addr);
                        goto begin_ejtag_dma_write_b;
-               } else  printf("DMA Write Addr = %08x  Data = ERROR ON WRITE\n", addr);
+               }
+               else
+                       LOG_ERROR("DMA Write Addr = %08" PRIx32 "  Data = ERROR ON WRITE\n", addr);
                return ERROR_JTAG_DEVICE_ERROR;
        }
 
        return ERROR_OK;
 }
 
-int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf)
+int mips32_dmaacc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
 {
        switch (size)
        {
                case 1:
-                       return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (u8*)buf);
+                       return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (uint8_t*)buf);
                case 2:
-                       return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (u16*)buf);
+                       return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (uint16_t*)buf);
                case 4:
-                       return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (u32*)buf);
+                       return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (uint32_t*)buf);
        }
 
        return ERROR_OK;
 }
 
-int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf)
+int mips32_dmaacc_read_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf)
 {
        int i;
        int     retval;
 
-       for(i=0; i<count; i++) {
-               if((retval=ejtag_dma_read(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
+       for (i = 0; i < count; i++) {
+               if ((retval = ejtag_dma_read(ejtag_info, addr + i*sizeof(*buf), &buf[i])) != ERROR_OK)
                        return retval;
        }
 
        return ERROR_OK;
 }
 
-int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
+int mips32_dmaacc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf)
 {
        int i;
        int retval;
 
-       for(i=0; i<count; i++) {
-               if((retval=ejtag_dma_read_h(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
+       for (i = 0; i < count; i++) {
+               if ((retval = ejtag_dma_read_h(ejtag_info, addr + i*sizeof(*buf), &buf[i])) != ERROR_OK)
                        return retval;
        }
 
        return ERROR_OK;
 }
 
-int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf)
+int mips32_dmaacc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf)
 {
        int i;
        int retval;
 
-       for(i=0; i<count; i++) {
-               if((retval=ejtag_dma_read_b(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
+       for (i = 0; i < count; i++) {
+               if ((retval = ejtag_dma_read_b(ejtag_info, addr + i*sizeof(*buf), &buf[i])) != ERROR_OK)
                        return retval;
        }
 
        return ERROR_OK;
 }
 
-int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf)
+int mips32_dmaacc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
 {
        switch (size)
        {
                case 1:
-                       return mips32_dmaacc_write_mem8(ejtag_info, addr, count, (u8*)buf);
+                       return mips32_dmaacc_write_mem8(ejtag_info, addr, count, (uint8_t*)buf);
                case 2:
-                       return mips32_dmaacc_write_mem16(ejtag_info, addr, count,(u16*)buf);
+                       return mips32_dmaacc_write_mem16(ejtag_info, addr, count,(uint16_t*)buf);
                case 4:
-                       return mips32_dmaacc_write_mem32(ejtag_info, addr, count, (u32*)buf);
+                       return mips32_dmaacc_write_mem32(ejtag_info, addr, count, (uint32_t*)buf);
        }
 
        return ERROR_OK;
 }
 
-int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf)
+int mips32_dmaacc_write_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf)
 {
        int i;
        int retval;
 
-       for(i=0; i<count; i++) {
-               if((retval=ejtag_dma_write(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
+       for (i = 0; i < count; i++) {
+               if ((retval = ejtag_dma_write(ejtag_info, addr + i*sizeof(*buf), buf[i])) != ERROR_OK)
                        return retval;
        }
 
        return ERROR_OK;
 }
 
-int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
+int mips32_dmaacc_write_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf)
 {
        int i;
        int retval;
 
-       for(i=0; i<count; i++) {
-               if((retval=ejtag_dma_write_h(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
+       for (i = 0; i < count; i++) {
+               if ((retval = ejtag_dma_write_h(ejtag_info, addr + i*sizeof(*buf), buf[i])) != ERROR_OK)
                        return retval;
        }
 
        return ERROR_OK;
 }
 
-int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf)
+int mips32_dmaacc_write_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf)
 {
        int i;
        int retval;
 
-       for(i=0; i<count; i++) {
-               if((retval=ejtag_dma_write_b(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
+       for (i = 0; i < count; i++) {
+               if ((retval = ejtag_dma_write_b(ejtag_info, addr + i*sizeof(*buf), buf[i])) != ERROR_OK)
                        return retval;
        }
 
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)