ARMv7-M: make DAP commands verify target is an ARMv7-M

[openocd.git] / src / target / mips32.h

diff --git a/src/target/mips32.h b/src/target/mips32.h
index 7d1928e5b057781d7b657aaaa33864fd4b425952..b731c686edc469ee34fc803f9216e6a6e5f4d32d 100644 (file)
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -26,7 +26,6 @@
 #include "target.h"
 #include "mips32_pracc.h"
 
-
 #define MIPS32_COMMON_MAGIC            0xB320B320
 
 /* offsets into mips32 core register cache */
@@ -36,10 +35,17 @@ enum
        MIPS32NUMCOREREGS
 };
 
+enum mips32_isa_mode
+{
+       MIPS32_ISA_MIPS32 = 0,
+       MIPS32_ISA_MIPS16E = 1,
+};
+
+extern const char *mips_isa_strings[];
+
 struct mips32_comparator
 {
        int used;
-       //int type;
        uint32_t bp_value;
        uint32_t reg_address;
 };
@@ -51,6 +57,7 @@ struct mips32_common
        struct reg_cache *core_cache;
        struct mips_ejtag ejtag_info;
        uint32_t core_regs[MIPS32NUMCOREREGS];
+       enum mips32_isa_mode isa_mode;
 
        int bp_scanned;
        int num_inst_bpoints;
@@ -65,6 +72,12 @@ struct mips32_common
        int (*write_core_reg)(struct target *target, int num);
 };
 
+static inline struct mips32_common *
+target_to_mips32(struct target *target)
+{
+       return target->arch_info;
+}
+
 struct mips32_core_reg
 {
        uint32_t num;
@@ -77,6 +90,7 @@ struct mips32_core_reg
 #define MIPS32_OP_ADDI 0x08
 #define MIPS32_OP_AND  0x24
 #define MIPS32_OP_COP0 0x10
+#define MIPS32_OP_JR   0x08
 #define MIPS32_OP_LUI  0x0F
 #define MIPS32_OP_LW   0x23
 #define MIPS32_OP_LBU  0x24
@@ -103,6 +117,7 @@ struct mips32_core_reg
 #define MIPS32_B(off)                          MIPS32_BEQ(0, 0, off)
 #define MIPS32_BEQ(src,tar,off)                MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
 #define MIPS32_BNE(src,tar,off)                MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
+#define MIPS32_JR(reg)                         MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR)
 #define MIPS32_MFC0(gpr, cpr, sel)     MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
 #define MIPS32_MTC0(gpr,cpr, sel)      MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
 #define MIPS32_LBU(reg, off, base)     MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
@@ -121,7 +136,7 @@ struct mips32_core_reg
 /* ejtag specific instructions */
 #define MIPS32_DRET                                    0x4200001F
 #define MIPS32_SDBBP                           0x7000003F
-#define MIPS16_SDBBP                           0xE801
+#define MIPS16_SDBBP                           0xE801
 
 int mips32_arch_state(struct target *target);