ARMv7-M: make DAP commands verify target is an ARMv7-M

[openocd.git] / src / target / mips32.h

diff --git a/src/target/mips32.h b/src/target/mips32.h
index 64328e3519b03a6b24067732a54322bf81bef6c4..b731c686edc469ee34fc803f9216e6a6e5f4d32d 100644 (file)
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -24,10 +24,8 @@
 #define MIPS32_H
 
 #include "target.h"
-#include "register.h"
 #include "mips32_pracc.h"
 
-
 #define MIPS32_COMMON_MAGIC            0xB320B320
 
 /* offsets into mips32 core register cache */
@@ -37,47 +35,62 @@ enum
        MIPS32NUMCOREREGS
 };
 
-typedef struct mips32_comparator_s
+enum mips32_isa_mode
+{
+       MIPS32_ISA_MIPS32 = 0,
+       MIPS32_ISA_MIPS16E = 1,
+};
+
+extern const char *mips_isa_strings[];
+
+struct mips32_comparator
 {
        int used;
-       //int type;
        uint32_t bp_value;
        uint32_t reg_address;
-} mips32_comparator_t;
+};
 
-typedef struct mips32_common_s
+struct mips32_common
 {
        uint32_t common_magic;
        void *arch_info;
-       reg_cache_t *core_cache;
-       mips_ejtag_t ejtag_info;
+       struct reg_cache *core_cache;
+       struct mips_ejtag ejtag_info;
        uint32_t core_regs[MIPS32NUMCOREREGS];
+       enum mips32_isa_mode isa_mode;
 
        int bp_scanned;
        int num_inst_bpoints;
        int num_data_bpoints;
        int num_inst_bpoints_avail;
        int num_data_bpoints_avail;
-       mips32_comparator_t *inst_break_list;
-       mips32_comparator_t *data_break_list;
+       struct mips32_comparator *inst_break_list;
+       struct mips32_comparator *data_break_list;
 
        /* register cache to processor synchronization */
-       int (*read_core_reg)(struct target_s *target, int num);
-       int (*write_core_reg)(struct target_s *target, int num);
-} mips32_common_t;
+       int (*read_core_reg)(struct target *target, int num);
+       int (*write_core_reg)(struct target *target, int num);
+};
 
-typedef struct mips32_core_reg_s
+static inline struct mips32_common *
+target_to_mips32(struct target *target)
+{
+       return target->arch_info;
+}
+
+struct mips32_core_reg
 {
        uint32_t num;
-       struct target_s *target;
-       mips32_common_t *mips32_common;
-} mips32_core_reg_t;
+       struct target *target;
+       struct mips32_common *mips32_common;
+};
 
 #define MIPS32_OP_BEQ  0x04
 #define MIPS32_OP_BNE  0x05
 #define MIPS32_OP_ADDI 0x08
 #define MIPS32_OP_AND  0x24
 #define MIPS32_OP_COP0 0x10
+#define MIPS32_OP_JR   0x08
 #define MIPS32_OP_LUI  0x0F
 #define MIPS32_OP_LW   0x23
 #define MIPS32_OP_LBU  0x24
@@ -104,6 +117,7 @@ typedef struct mips32_core_reg_s
 #define MIPS32_B(off)                          MIPS32_BEQ(0, 0, off)
 #define MIPS32_BEQ(src,tar,off)                MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
 #define MIPS32_BNE(src,tar,off)                MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
+#define MIPS32_JR(reg)                         MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR)
 #define MIPS32_MFC0(gpr, cpr, sel)     MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
 #define MIPS32_MTC0(gpr,cpr, sel)      MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
 #define MIPS32_LBU(reg, off, base)     MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
@@ -122,34 +136,33 @@ typedef struct mips32_core_reg_s
 /* ejtag specific instructions */
 #define MIPS32_DRET                                    0x4200001F
 #define MIPS32_SDBBP                           0x7000003F
-#define MIPS16_SDBBP                           0xE801
+#define MIPS16_SDBBP                           0xE801
 
-int mips32_arch_state(struct target_s *target);
+int mips32_arch_state(struct target *target);
 
-int mips32_init_arch_info(target_t *target,
-               mips32_common_t *mips32, struct jtag_tap *tap);
+int mips32_init_arch_info(struct target *target,
+               struct mips32_common *mips32, struct jtag_tap *tap);
 
-int mips32_restore_context(target_t *target);
-int mips32_save_context(target_t *target);
+int mips32_restore_context(struct target *target);
+int mips32_save_context(struct target *target);
 
-reg_cache_t *mips32_build_reg_cache(target_t *target);
+struct reg_cache *mips32_build_reg_cache(struct target *target);
 
-int mips32_run_algorithm(struct target_s *target,
-               int num_mem_params, mem_param_t *mem_params,
-               int num_reg_params, reg_param_t *reg_params,
+int mips32_run_algorithm(struct target *target,
+               int num_mem_params, struct mem_param *mem_params,
+               int num_reg_params, struct reg_param *reg_params,
                uint32_t entry_point, uint32_t exit_point,
                int timeout_ms, void *arch_info);
 
-int mips32_configure_break_unit(struct target_s *target);
+int mips32_configure_break_unit(struct target *target);
 
-int mips32_enable_interrupts(struct target_s *target, int enable);
+int mips32_enable_interrupts(struct target *target, int enable);
 
-int mips32_examine(struct target_s *target);
+int mips32_examine(struct target *target);
 
-int mips32_register_commands(struct command_context_s *cmd_ctx);
+int mips32_register_commands(struct command_context *cmd_ctx);
 
-int mips32_invalidate_core_regs(target_t *target);
-int mips32_get_gdb_reg_list(target_t *target,
-               reg_t **reg_list[], int *reg_list_size);
+int mips32_get_gdb_reg_list(struct target *target,
+               struct reg **reg_list[], int *reg_list_size);
 
 #endif /*MIPS32_H*/