ARM7/ARM9: help/usage updates

[openocd.git] / src / target / mips32.h

diff --git a/src/target/mips32.h b/src/target/mips32.h
index 98186aff93cf507e8432ca15d14f31b8b428d5a8..4fe61bcdedf4569e386bd40117caba2d6f167513 100644 (file)
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -23,8 +23,8 @@
 #ifndef MIPS32_H
 #define MIPS32_H
 
-#include <target/target.h>
-#include <target/mips32_pracc.h>
+#include "target.h"
+#include "mips32_pracc.h"
 
 
 #define MIPS32_COMMON_MAGIC            0xB320B320
@@ -77,6 +77,7 @@ struct mips32_core_reg
 #define MIPS32_OP_ADDI 0x08
 #define MIPS32_OP_AND  0x24
 #define MIPS32_OP_COP0 0x10
+#define MIPS32_OP_JR   0x08
 #define MIPS32_OP_LUI  0x0F
 #define MIPS32_OP_LW   0x23
 #define MIPS32_OP_LBU  0x24
@@ -103,6 +104,7 @@ struct mips32_core_reg
 #define MIPS32_B(off)                          MIPS32_BEQ(0, 0, off)
 #define MIPS32_BEQ(src,tar,off)                MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
 #define MIPS32_BNE(src,tar,off)                MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
+#define MIPS32_JR(reg)                         MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR)
 #define MIPS32_MFC0(gpr, cpr, sel)     MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
 #define MIPS32_MTC0(gpr,cpr, sel)      MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
 #define MIPS32_LBU(reg, off, base)     MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
@@ -121,7 +123,7 @@ struct mips32_core_reg
 /* ejtag specific instructions */
 #define MIPS32_DRET                                    0x4200001F
 #define MIPS32_SDBBP                           0x7000003F
-#define MIPS16_SDBBP                           0xE801
+#define MIPS16_SDBBP                           0xE801
 
 int mips32_arch_state(struct target *target);