aarch64: support for aarch32 ARM_MODE_SYS

[openocd.git] / src / target / lakemont.h

diff --git a/src/target/lakemont.h b/src/target/lakemont.h
index e63cab027805a19f72db1979a6315dd5f86a405f..98efd44a996e7cf1e49671a936c228bac4df61c4 100644 (file)
--- a/src/target/lakemont.h
+++ b/src/target/lakemont.h
@@ -1,5 +1,5 @@
 /*
- * Copyright(c) 2013 Intel Corporation.
+ * Copyright(c) 2013-2016 Intel Corporation.
  *
  * Adrian Burns (adrian.burns@intel.com)
  * Thomas Faust (thomas.faust@intel.com)
@@ -8,8 +8,9 @@
  * Jeffrey Maxwell (jeffrey.r.maxwell@intel.com)
  *
  * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful, but
  * WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -17,8 +18,7 @@
  * General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  *
  * Contact Information:
  * Intel Corporation
@@ -29,9 +29,11 @@
  * This is the interface to the probemode operations for Lakemont 1 (LMT1).
  */
 
-#ifndef LAKEMONT_H
-#define LAKEMONT_H
+#ifndef OPENOCD_TARGET_LAKEMONT_H
+#define OPENOCD_TARGET_LAKEMONT_H
+
 #include <jtag/jtag.h>
+#include <helper/types.h>
 
 /* The Intel Quark SoC X1000 Core is codenamed lakemont */
 
@@ -59,18 +61,18 @@
 /* needed during lakemont probemode */
 #define NOT_PMREG              0xfe
 #define NOT_AVAIL_REG          0xff
-#define PM_DSB                 0x00000000
-#define PM_DSL                 0xFFFFFFFF
-#define PM_DSAR                        0x004F9300
-#define PM_DR7                 0x00000400
+#define PM_DSB                 ((uint32_t)0x00000000)
+#define PM_DSL                 ((uint32_t)0xFFFFFFFF)
+#define PM_DSAR                        ((uint32_t)0x004F9300)
+#define PM_DR7                 ((uint32_t)0x00000400)
 #define DELAY_SUBMITPIR                0 /* for now 0 is working */
 
 /* lakemont tapstatus bits */
-#define TS_PRDY_BIT            0x00000001
-#define TS_EN_PM_BIT           0x00000002
-#define TS_PM_BIT              0x00000004
-#define TS_PMCR_BIT            0x00000008
-#define TS_SBP_BIT             0x00000010
+#define TS_PRDY_BIT            ((uint32_t)0x00000001)
+#define TS_EN_PM_BIT           ((uint32_t)0x00000002)
+#define TS_PM_BIT              ((uint32_t)0x00000004)
+#define TS_PMCR_BIT            ((uint32_t)0x00000008)
+#define TS_SBP_BIT             ((uint32_t)0x00000010)
 
 struct lakemont_core_reg {
        uint32_t num;
@@ -93,11 +95,12 @@ int lakemont_init_arch_info(struct target *t, struct x86_32_common *x86_32);
 int lakemont_poll(struct target *t);
 int lakemont_arch_state(struct target *t);
 int lakemont_halt(struct target *t);
-int lakemont_resume(struct target *t, int current, uint32_t address,
+int lakemont_resume(struct target *t, int current, target_addr_t address,
                        int handle_breakpoints, int debug_execution);
 int lakemont_step(struct target *t, int current,
-                       uint32_t address, int handle_breakpoints);
+                       target_addr_t address, int handle_breakpoints);
 int lakemont_reset_assert(struct target *t);
 int lakemont_reset_deassert(struct target *t);
+int lakemont_update_after_probemode_entry(struct target *t);
 
-#endif /* LAKEMONT_H */
+#endif /* OPENOCD_TARGET_LAKEMONT_H */