}
for (i = 0; i < (x86_32->cache->num_regs); i++) {
- x86_32->cache->reg_list[i].dirty = 0;
- x86_32->cache->reg_list[i].valid = 0;
+ x86_32->cache->reg_list[i].dirty = false;
+ x86_32->cache->reg_list[i].valid = false;
}
return err;
}
if (check_not_halted(t))
return ERROR_TARGET_NOT_HALTED;
buf_set_u32(reg->value, 0, 32, value);
- reg->dirty = 1;
- reg->valid = 1;
+ reg->dirty = true;
+ reg->valid = true;
return ERROR_OK;
}
reg_list[i].name = regs[i].name;
reg_list[i].size = 32;
reg_list[i].value = calloc(1, 4);
- reg_list[i].dirty = 0;
- reg_list[i].valid = 0;
+ reg_list[i].dirty = false;
+ reg_list[i].valid = false;
reg_list[i].type = &lakemont_reg_type;
reg_list[i].arch_info = &arch_info[i];
*regval = buf_get_u32(scan.out, 0, 32);
if (cache) {
buf_set_u32(x86_32->cache->reg_list[reg].value, 0, 32, *regval);
- x86_32->cache->reg_list[reg].valid = 1;
- x86_32->cache->reg_list[reg].dirty = 0;
+ x86_32->cache->reg_list[reg].valid = true;
+ x86_32->cache->reg_list[reg].dirty = false;
}
LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32,
x86_32->cache->reg_list[reg].name,
/* we are writing from the cache so ensure we reset flags */
if (cache) {
- x86_32->cache->reg_list[reg].dirty = 0;
- x86_32->cache->reg_list[reg].valid = 0;
+ x86_32->cache->reg_list[reg].dirty = false;
+ x86_32->cache->reg_list[reg].valid = false;
}
return ERROR_OK;
}
* breakpoint instruction. This needs to be corrected.
*/
buf_set_u32(x86_32->cache->reg_list[EIP].value, 0, 32, eip-1);
- x86_32->cache->reg_list[EIP].dirty = 1;
- x86_32->cache->reg_list[EIP].valid = 1;
+ x86_32->cache->reg_list[EIP].dirty = true;
+ x86_32->cache->reg_list[EIP].valid = true;
LOG_USER("hit software breakpoint at 0x%08" PRIx32, eip-1);
} else {
/* it's not a hardware breakpoint (checked already in DR6 state)