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Sten <debian@sansys-electronic.com>: add support for Olimex LPC2378STK eval board.
[openocd.git] / src / target / etm.c
diff --git a/src/target/etm.c b/src/target/etm.c
index b07f1a75ae2ef95268229bcaa83c4ed7e420b916..f95907099ac9e210e153fb674d900b44265c1fc5 100644 (file)
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -208,11 +208,6 @@ char* etm_reg_list[] =
 int etm_reg_arch_type = -1;
 
 int etm_get_reg(reg_t *reg);
-int etm_set_reg(reg_t *reg, u32 value);
-int etm_set_reg_w_exec(reg_t *reg, u8 *buf);
-
-int etm_write_reg(reg_t *reg, u32 value);
-int etm_read_reg(reg_t *reg);
 
 command_t *etm_cmd = NULL;
 
@@ -311,15 +306,17 @@ int etm_setup(target_t *target)
 
 int etm_get_reg(reg_t *reg)
 {
-       if (etm_read_reg(reg) != ERROR_OK)
+       int retval;
+       if ((retval = etm_read_reg(reg)) != ERROR_OK)
        {
                LOG_ERROR("BUG: error scheduling etm register read");
-               exit(-1);
+               return retval;
        }
 
-       if (jtag_execute_queue() != ERROR_OK)
+       if ((retval = jtag_execute_queue()) != ERROR_OK)
        {
                LOG_ERROR("register read failed");
+               return retval;
        }
 
        return ERROR_OK;
@@ -333,11 +330,11 @@ int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 
        LOG_DEBUG("%i", etm_reg->addr);
 
-       jtag_add_end_state(TAP_RTI);
+       jtag_add_end_state(TAP_IDLE);
        arm_jtag_scann(etm_reg->jtag_info, 0x6);
        arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 
-       fields[0].device = etm_reg->jtag_info->chain_pos;
+       fields[0].tap = etm_reg->jtag_info->tap;
        fields[0].num_bits = 32;
        fields[0].out_value = reg->value;
        fields[0].out_mask = NULL;
@@ -347,7 +344,7 @@ int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
        fields[0].in_handler = NULL;
        fields[0].in_handler_priv = NULL;
 
-       fields[1].device = etm_reg->jtag_info->chain_pos;
+       fields[1].tap = etm_reg->jtag_info->tap;
        fields[1].num_bits = 7;
        fields[1].out_value = malloc(1);
        buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
@@ -358,7 +355,7 @@ int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
        fields[1].in_handler = NULL;
        fields[1].in_handler_priv = NULL;
 
-       fields[2].device = etm_reg->jtag_info->chain_pos;
+       fields[2].tap = etm_reg->jtag_info->tap;
        fields[2].num_bits = 1;
        fields[2].out_value = malloc(1);
        buf_set_u32(fields[2].out_value, 0, 1, 0);
@@ -369,12 +366,12 @@ int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
        fields[2].in_handler = NULL;
        fields[2].in_handler_priv = NULL;
 
-       jtag_add_dr_scan(3, fields, -1);
+       jtag_add_dr_scan(3, fields, TAP_INVALID);
 
        fields[0].in_value = reg->value;
        jtag_set_check_value(fields+0, check_value, check_mask, NULL);
 
-       jtag_add_dr_scan(3, fields, -1);
+       jtag_add_dr_scan(3, fields, TAP_INVALID);
 
        free(fields[1].out_value);
        free(fields[2].out_value);
@@ -389,10 +386,11 @@ int etm_read_reg(reg_t *reg)
 
 int etm_set_reg(reg_t *reg, u32 value)
 {
-       if (etm_write_reg(reg, value) != ERROR_OK)
+       int retval;
+       if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
        {
                LOG_ERROR("BUG: error scheduling etm register write");
-               exit(-1);
+               return retval;
        }
 
        buf_set_u32(reg->value, 0, reg->size, value);
@@ -404,12 +402,13 @@ int etm_set_reg(reg_t *reg, u32 value)
 
 int etm_set_reg_w_exec(reg_t *reg, u8 *buf)
 {
+       int retval;
        etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 
-       if (jtag_execute_queue() != ERROR_OK)
+       if ((retval = jtag_execute_queue()) != ERROR_OK)
        {
                LOG_ERROR("register write failed");
-               exit(-1);
+               return retval;
        }
        return ERROR_OK;
 }
@@ -422,11 +421,11 @@ int etm_write_reg(reg_t *reg, u32 value)
 
        LOG_DEBUG("%i: 0x%8.8x", etm_reg->addr, value);
 
-       jtag_add_end_state(TAP_RTI);
+       jtag_add_end_state(TAP_IDLE);
        arm_jtag_scann(etm_reg->jtag_info, 0x6);
        arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 
-       fields[0].device = etm_reg->jtag_info->chain_pos;
+       fields[0].tap = etm_reg->jtag_info->tap;
        fields[0].num_bits = 32;
        fields[0].out_value = malloc(4);
        buf_set_u32(fields[0].out_value, 0, 32, value);
@@ -437,7 +436,7 @@ int etm_write_reg(reg_t *reg, u32 value)
        fields[0].in_handler = NULL;
        fields[0].in_handler_priv = NULL;
 
-       fields[1].device = etm_reg->jtag_info->chain_pos;
+       fields[1].tap = etm_reg->jtag_info->tap;
        fields[1].num_bits = 7;
        fields[1].out_value = malloc(1);
        buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
@@ -448,7 +447,7 @@ int etm_write_reg(reg_t *reg, u32 value)
        fields[1].in_handler = NULL;
        fields[1].in_handler_priv = NULL;
 
-       fields[2].device = etm_reg->jtag_info->chain_pos;
+       fields[2].tap = etm_reg->jtag_info->tap;
        fields[2].num_bits = 1;
        fields[2].out_value = malloc(1);
        buf_set_u32(fields[2].out_value, 0, 1, 1);
@@ -459,7 +458,7 @@ int etm_write_reg(reg_t *reg, u32 value)
        fields[2].in_handler = NULL;
        fields[2].in_handler_priv = NULL;
 
-       jtag_add_dr_scan(3, fields, -1);
+       jtag_add_dr_scan(3, fields, TAP_INVALID);
 
        free(fields[0].out_value);
        free(fields[1].out_value);
@@ -476,7 +475,6 @@ int etm_store_reg(reg_t *reg)
 /* ETM trace analysis functionality
  *
  */
-extern etm_capture_driver_t etb_capture_driver;
 extern etm_capture_driver_t etm_dummy_capture_driver;
 #if BUILD_OOCD_TRACE == 1
 extern etm_capture_driver_t oocd_trace_capture_driver;
@@ -643,7 +641,7 @@ int etmv1_branch_address(etm_context_t *ctx)
        u8 packet;
        int shift = 0;
        int apo;
-       int i;
+       u32 i;
 
        /* quit analysis if less than two cycles are left in the trace
         * because we can't extract the APO */
@@ -879,7 +877,7 @@ int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
                                continue;
 
                        /* indirect branch to the exception vector means an exception occured */
-                       if (((ctx->last_branch >= 0x0) && (ctx->last_branch <= 0x20))
+                       if ((ctx->last_branch <= 0x20)
                                || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
                        {
                                if ((ctx->last_branch & 0xff) == 0x10)
@@ -994,7 +992,7 @@ int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
                        if (((instruction.type == ARM_B) ||
                                (instruction.type == ARM_BL) ||
                                (instruction.type == ARM_BLX)) &&
-                               (instruction.info.b_bl_bx_blx.target_address != -1))
+                               (instruction.info.b_bl_bx_blx.target_address != ~0UL))
                        {
                                next_pc = instruction.info.b_bl_bx_blx.target_address;
                        }
@@ -1539,7 +1537,7 @@ int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd, char *
        armv4_5_common_t *armv4_5;
        arm7_9_common_t *arm7_9;
        etm_context_t *etm_ctx;
-       int i;
+       u32 i;
 
        if (argc != 1)
        {
@@ -1607,7 +1605,7 @@ int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, char *
        armv4_5_common_t *armv4_5;
        arm7_9_common_t *arm7_9;
        etm_context_t *etm_ctx;
-       int i;
+       u32 i;
 
        if (argc != 1)
        {
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