+static const struct command_registration etb_config_command_handlers[] = {
+ {
+ .name = "config",
+ .handler = &handle_etb_config_command,
+ .mode = COMMAND_CONFIG,
+ .usage = "<target> <tap>",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration etb_command_handlers[] = {
+ {
+ .name = "etb",
+ .mode = COMMAND_ANY,
+ .help = "Emebdded Trace Buffer command group",
+ .chain = etb_config_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+static int etb_init(struct etm_context *etm_ctx)
+{
+ struct etb *etb = etm_ctx->capture_driver_priv;
+
+ etb->etm_ctx = etm_ctx;
+
+ /* identify ETB RAM depth and width */
+ etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
+ etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
+ jtag_execute_queue();
+
+ etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
+ etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
+
+ return ERROR_OK;
+}
+
+static trace_status_t etb_status(struct etm_context *etm_ctx)
+{
+ struct etb *etb = etm_ctx->capture_driver_priv;
+ struct reg *control = &etb->reg_cache->reg_list[ETB_CTRL];
+ struct reg *status = &etb->reg_cache->reg_list[ETB_STATUS];
+ trace_status_t retval = 0;
+ int etb_timeout = 100;
+
+ etb->etm_ctx = etm_ctx;
+
+ /* read control and status registers */
+ etb_read_reg(control);
+ etb_read_reg(status);
+ jtag_execute_queue();
+
+ /* See if it's (still) active */
+ retval = buf_get_u32(control->value, 0, 1) ? TRACE_RUNNING : TRACE_IDLE;
+
+ /* check Full bit to identify wraparound/overflow */
+ if (buf_get_u32(status->value, 0, 1) == 1)
+ retval |= TRACE_OVERFLOWED;
+
+ /* check Triggered bit to identify trigger condition */
+ if (buf_get_u32(status->value, 1, 1) == 1)
+ retval |= TRACE_TRIGGERED;
+
+ /* check AcqComp to see if trigger counter dropped to zero */
+ if (buf_get_u32(status->value, 2, 1) == 1) {
+ /* wait for DFEmpty */
+ while (etb_timeout-- && buf_get_u32(status->value, 3, 1) == 0)
+ etb_get_reg(status);
+
+ if (etb_timeout == 0)
+ LOG_ERROR("ETB: DFEmpty won't go high, status 0x%02x",
+ (unsigned) buf_get_u32(status->value, 0, 4));
+
+ if (!(etm_ctx->capture_status & TRACE_TRIGGERED))
+ LOG_WARNING("ETB: trace complete without triggering?");
+
+ retval |= TRACE_COMPLETED;
+ }
+
+ /* NOTE: using a trigger is optional; and at least ETB11 has a mode
+ * where it can ignore the trigger counter.
+ */
+
+ /* update recorded state */
+ etm_ctx->capture_status = retval;
+
+ return retval;
+}
+
+static int etb_read_trace(struct etm_context *etm_ctx)
+{
+ struct etb *etb = etm_ctx->capture_driver_priv;
+ int first_frame = 0;
+ int num_frames = etb->ram_depth;
+ uint32_t *trace_data = NULL;
+ int i, j;
+
+ etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
+ etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
+ jtag_execute_queue();
+
+ /* check if we overflowed, and adjust first frame of the trace accordingly
+ * if we didn't overflow, read only up to the frame that would be written next,
+ * i.e. don't read invalid entries
+ */
+ if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
+ {
+ first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
+ }
+ else
+ {
+ num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
+ }
+
+ etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
+
+ /* read data into temporary array for unpacking */
+ trace_data = malloc(sizeof(uint32_t) * num_frames);
+ etb_read_ram(etb, trace_data, num_frames);
+
+ if (etm_ctx->trace_depth > 0)
+ {
+ free(etm_ctx->trace_data);
+ }
+
+ if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
+ etm_ctx->trace_depth = num_frames * 3;
+ else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
+ etm_ctx->trace_depth = num_frames * 2;
+ else
+ etm_ctx->trace_depth = num_frames;
+
+ etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
+
+ for (i = 0, j = 0; i < num_frames; i++)
+ {
+ if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
+ {
+ /* trace word j */
+ etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
+ etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
+ etm_ctx->trace_data[j].flags = 0;
+ if ((trace_data[i] & 0x80) >> 7)
+ {
+ etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
+ }
+ if (etm_ctx->trace_data[j].pipestat == STAT_TR)
+ {
+ etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
+ etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
+ }
+
+ /* trace word j + 1 */
+ etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x100) >> 8;
+ etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7800) >> 11;
+ etm_ctx->trace_data[j + 1].flags = 0;
+ if ((trace_data[i] & 0x8000) >> 15)
+ {
+ etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
+ }
+ if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
+ {
+ etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
+ etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
+ }
+
+ /* trace word j + 2 */
+ etm_ctx->trace_data[j + 2].pipestat = (trace_data[i] & 0x10000) >> 16;
+ etm_ctx->trace_data[j + 2].packet = (trace_data[i] & 0x780000) >> 19;
+ etm_ctx->trace_data[j + 2].flags = 0;
+ if ((trace_data[i] & 0x800000) >> 23)
+ {
+ etm_ctx->trace_data[j + 2].flags |= ETMV1_TRACESYNC_CYCLE;
+ }
+ if (etm_ctx->trace_data[j + 2].pipestat == STAT_TR)
+ {
+ etm_ctx->trace_data[j + 2].pipestat = etm_ctx->trace_data[j + 2].packet & 0x7;
+ etm_ctx->trace_data[j + 2].flags |= ETMV1_TRIGGER_CYCLE;
+ }
+
+ j += 3;
+ }
+ else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
+ {
+ /* trace word j */
+ etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
+ etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
+ etm_ctx->trace_data[j].flags = 0;
+ if ((trace_data[i] & 0x800) >> 11)
+ {
+ etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
+ }
+ if (etm_ctx->trace_data[j].pipestat == STAT_TR)
+ {
+ etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
+ etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
+ }
+
+ /* trace word j + 1 */
+ etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x7000) >> 12;
+ etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7f8000) >> 15;
+ etm_ctx->trace_data[j + 1].flags = 0;
+ if ((trace_data[i] & 0x800000) >> 23)
+ {
+ etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
+ }
+ if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
+ {
+ etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
+ etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
+ }
+
+ j += 2;
+ }
+ else
+ {
+ /* trace word j */
+ etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
+ etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
+ etm_ctx->trace_data[j].flags = 0;
+ if ((trace_data[i] & 0x80000) >> 19)
+ {
+ etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
+ }
+ if (etm_ctx->trace_data[j].pipestat == STAT_TR)
+ {
+ etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
+ etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
+ }
+
+ j += 1;
+ }
+ }
+
+ free(trace_data);
+
+ return ERROR_OK;
+}
+
+static int etb_start_capture(struct etm_context *etm_ctx)
+{
+ struct etb *etb = etm_ctx->capture_driver_priv;
+ uint32_t etb_ctrl_value = 0x1;
+ uint32_t trigger_count;
+
+ if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
+ {
+ if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
+ {
+ LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
+ return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
+ }
+ etb_ctrl_value |= 0x2;
+ }
+
+ if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED) {
+ LOG_ERROR("ETB: can't run in multiplexed mode");
+ return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
+ }
+
+ trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;
+
+ etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
+ etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
+ etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
+ jtag_execute_queue();
+
+ /* we're starting a new trace, initialize capture status */
+ etm_ctx->capture_status = TRACE_RUNNING;
+
+ return ERROR_OK;
+}
+
+static int etb_stop_capture(struct etm_context *etm_ctx)
+{
+ struct etb *etb = etm_ctx->capture_driver_priv;
+ struct reg *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
+
+ etb_write_reg(etb_ctrl_reg, 0x0);
+ jtag_execute_queue();
+
+ /* trace stopped, just clear running flag, but preserve others */
+ etm_ctx->capture_status &= ~TRACE_RUNNING;
+
+ return ERROR_OK;
+}
+
+struct etm_capture_driver etb_capture_driver =
+{
+ .name = "etb",
+ .commands = etb_command_handlers,
+ .init = etb_init,
+ .status = etb_status,
+ .start_capture = etb_start_capture,
+ .stop_capture = etb_stop_capture,
+ .read_trace = etb_read_trace,
+};