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update files to correct FSF address
[openocd.git] / src / target / embeddedice.c
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 4693fcc2274390e900b1103ea45882ebd43f345e..016883086c835c94c1bc3e8c72ba5500fcdf1aa1 100644 (file)
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -2,7 +2,7 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
  *                                                                         *
- *   Copyright (C) 2007,2008,2009 Øyvind Harboe                            *
+ *   Copyright (C) 2007-2010 Øyvind Harboe                                 *
  *   oyvind.harboe@zylin.com                                               *
  *                                                                         *
  *   Copyright (C) 2008 by Spencer Oliver                                  *
@@ -21,8 +21,9 @@
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  ***************************************************************************/
+
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
@@ -47,6 +48,8 @@
  * core entered debug mode.
  */
 
+static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf);
+
 /*
  * From:  ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores)
  */
@@ -85,7 +88,7 @@ static const struct {
                .addr =         9,
                .width =        32,
        },
-       [EICE_W0_DATA_VALUE ] = {
+       [EICE_W0_DATA_VALUE] = {
                .name =         "watch_0_data_value",
                .addr =         10,
                .width =        32,
@@ -143,14 +146,16 @@ static const struct {
        },
 };
 
-
 static int embeddedice_get_reg(struct reg *reg)
 {
-       int retval;
-
-       if ((retval = embeddedice_read_reg(reg)) != ERROR_OK)
+       int retval = embeddedice_read_reg(reg);
+       if (retval != ERROR_OK) {
                LOG_ERROR("error queueing EmbeddedICE register read");
-       else if ((retval = jtag_execute_queue()) != ERROR_OK)
+               return retval;
+       }
+
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
                LOG_ERROR("EmbeddedICE register read failed");
 
        return retval;
@@ -166,8 +171,8 @@ static const struct reg_arch_type eice_reg_type = {
  * Different versions of the modules have different capabilities, such as
  * hardware support for vector_catch, single stepping, and monitor mode.
  */
-struct reg_cache *
-embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
+struct reg_cache *embeddedice_build_reg_cache(struct target *target,
+               struct arm7_9_common *arm7_9)
 {
        int retval;
        struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
@@ -198,8 +203,7 @@ embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
         */
 
        /* set up registers */
-       for (i = 0; i < num_regs; i++)
-       {
+       for (i = 0; i < num_regs; i++) {
                reg_list[i].name = eice_regs[i].name;
                reg_list[i].size = eice_regs[i].width;
                reg_list[i].dirty = 0;
@@ -213,12 +217,10 @@ embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
 
        /* identify EmbeddedICE version by reading DCC control register */
        embeddedice_read_reg(&reg_list[EICE_COMMS_CTRL]);
-       if ((retval = jtag_execute_queue()) != ERROR_OK)
-       {
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK) {
                for (i = 0; i < num_regs; i++)
-               {
                        free(reg_list[i].value);
-               }
                free(reg_list);
                free(reg_cache);
                free(arch_info);
@@ -228,8 +230,7 @@ embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
        eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
        LOG_INFO("Embedded ICE version %d", eice_version);
 
-       switch (eice_version)
-       {
+       switch (eice_version) {
                case 1:
                        /* ARM7TDMI r3, ARM7TDMI-S r3
                         *
@@ -288,7 +289,7 @@ embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
                         * and do the appropriate setup itself.
                         */
                        if (strcmp(target_type_name(target), "feroceon") == 0 ||
-                           strcmp(target_type_name(target), "dragonite") == 0)
+                                       strcmp(target_type_name(target), "dragonite") == 0)
                                break;
                        LOG_ERROR("unknown EmbeddedICE version "
                                "(comms ctrl: 0x%8.8" PRIx32 ")",
@@ -316,12 +317,12 @@ int embeddedice_setup(struct target *target)
         * that manages break requests.  ARM's "Angel Debug Monitor" is one
         * common example of such code.
         */
-       if (arm7_9->has_monitor_mode)
-       {
+       if (arm7_9->has_monitor_mode) {
                struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
                embeddedice_read_reg(dbg_ctrl);
-               if ((retval = jtag_execute_queue()) != ERROR_OK)
+               retval = jtag_execute_queue();
+               if (retval != ERROR_OK)
                        return retval;
                buf_set_u32(dbg_ctrl->value, 4, 1, 0);
                embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
@@ -342,11 +343,16 @@ int embeddedice_read_reg_w_check(struct reg *reg,
        struct scan_field fields[3];
        uint8_t field1_out[1];
        uint8_t field2_out[1];
+       int retval;
 
-       jtag_set_end_state(TAP_IDLE);
-       arm_jtag_scann(ice_reg->jtag_info, 0x2);
+       retval = arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
-       arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
+       retval = arm_jtag_set_instr(ice_reg->jtag_info,
+                       ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        /* bits 31:0 -- data (ignored here) */
        fields[0].num_bits = 32;
@@ -358,7 +364,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
        /* bits 36:32 -- register */
        fields[1].num_bits = 5;
        fields[1].out_value = field1_out;
-       fields[1].out_value[0] = reg_addr;
+       field1_out[0] = reg_addr;
        fields[1].in_value = NULL;
        fields[1].check_value = NULL;
        fields[1].check_mask = NULL;
@@ -366,13 +372,13 @@ int embeddedice_read_reg_w_check(struct reg *reg,
        /* bit 37 -- 0/read */
        fields[2].num_bits = 1;
        fields[2].out_value = field2_out;
-       fields[2].out_value[0] = 0;
+       field2_out[0] = 0;
        fields[2].in_value = NULL;
        fields[2].check_value = NULL;
        fields[2].check_mask = NULL;
 
        /* traverse Update-DR, setting address for the next read */
-       jtag_add_dr_scan(ice_reg->jtag_info->tap, 3, fields, jtag_get_end_state());
+       jtag_add_dr_scan(ice_reg->jtag_info->tap, 3, fields, TAP_IDLE);
 
        /* bits 31:0 -- the data we're reading (and maybe checking) */
        fields[0].in_value = reg->value;
@@ -383,10 +389,10 @@ int embeddedice_read_reg_w_check(struct reg *reg,
         * EICE_COMMS_DATA would read the register twice
         * reading the control register is safe
         */
-       fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
+       field1_out[0] = eice_regs[EICE_COMMS_CTRL].addr;
 
        /* traverse Update-DR, reading but with no other side effects */
-       jtag_add_dr_scan_check(ice_reg->jtag_info->tap, 3, fields, jtag_get_end_state());
+       jtag_add_dr_scan_check(ice_reg->jtag_info->tap, 3, fields, TAP_IDLE);
 
        return ERROR_OK;
 }
@@ -404,10 +410,14 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
        struct scan_field fields[3];
        uint8_t field1_out[1];
        uint8_t field2_out[1];
+       int retval;
 
-       jtag_set_end_state(TAP_IDLE);
-       arm_jtag_scann(jtag_info, 0x2);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+       retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        fields[0].num_bits = 32;
        fields[0].out_value = NULL;
@@ -415,26 +425,25 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
 
        fields[1].num_bits = 5;
        fields[1].out_value = field1_out;
-       fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
+       field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
        fields[1].in_value = NULL;
 
        fields[2].num_bits = 1;
        fields[2].out_value = field2_out;
-       fields[2].out_value[0] = 0;
+       field2_out[0] = 0;
        fields[2].in_value = NULL;
 
-       jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
+       jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
 
-       while (size > 0)
-       {
+       while (size > 0) {
                /* when reading the last item, set the register address to the DCC control reg,
                 * to avoid reading additional data from the DCC data reg
                 */
                if (size == 1)
-                       fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
+                       field1_out[0] = eice_regs[EICE_COMMS_CTRL].addr;
 
                fields[0].in_value = (uint8_t *)data;
-               jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
+               jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
                jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)data);
 
                data++;
@@ -471,12 +480,13 @@ void embeddedice_set_reg(struct reg *reg, uint32_t value)
  * Write an EmbeddedICE register, updating the register cache.
  * Uses embeddedice_set_reg(); not queued.
  */
-int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
+static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 {
        int retval;
 
        embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
-       if ((retval = jtag_execute_queue()) != ERROR_OK)
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
                LOG_ERROR("register write failed");
        return retval;
 }
@@ -490,10 +500,9 @@ void embeddedice_write_reg(struct reg *reg, uint32_t value)
 
        LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
 
-       jtag_set_end_state(TAP_IDLE);
-       arm_jtag_scann(ice_reg->jtag_info, 0x2);
+       arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
 
-       arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
+       arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
 
        uint8_t reg_addr = ice_reg->addr & 0x1f;
        embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
@@ -522,10 +531,14 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
        uint8_t field0_out[4];
        uint8_t field1_out[1];
        uint8_t field2_out[1];
+       int retval;
 
-       jtag_set_end_state(TAP_IDLE);
-       arm_jtag_scann(jtag_info, 0x2);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+       retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        fields[0].num_bits = 32;
        fields[0].out_value = field0_out;
@@ -533,19 +546,18 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
 
        fields[1].num_bits = 5;
        fields[1].out_value = field1_out;
-       fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
+       field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
        fields[1].in_value = NULL;
 
        fields[2].num_bits = 1;
        fields[2].out_value = field2_out;
-       fields[2].out_value[0] = 1;
+       field2_out[0] = 1;
 
        fields[2].in_value = NULL;
 
-       while (size > 0)
-       {
-               buf_set_u32(fields[0].out_value, 0, 32, *data);
-               jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
+       while (size > 0) {
+               buf_set_u32(field0_out, 0, 32, *data);
+               jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
 
                data++;
                size--;
@@ -573,12 +585,17 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
                hsact = 1;
        else if (hsbit == EICE_COMM_CTRL_RBIT)
                hsact = 0;
-       else
-               return ERROR_INVALID_ARGUMENTS;
+       else {
+               LOG_ERROR("Invalid arguments");
+               return ERROR_COMMAND_SYNTAX_ERROR;
+       }
 
-       jtag_set_end_state(TAP_IDLE);
-       arm_jtag_scann(jtag_info, 0x2);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+       retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        fields[0].num_bits = 32;
        fields[0].out_value = NULL;
@@ -586,19 +603,20 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
 
        fields[1].num_bits = 5;
        fields[1].out_value = field1_out;
-       fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
+       field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
        fields[1].in_value = NULL;
 
        fields[2].num_bits = 1;
        fields[2].out_value = field2_out;
-       fields[2].out_value[0] = 0;
+       field2_out[0] = 0;
        fields[2].in_value = NULL;
 
-       jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
+       jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
        gettimeofday(&lap, NULL);
        do {
-               jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
-               if ((retval = jtag_execute_queue()) != ERROR_OK)
+               jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
+               retval = jtag_execute_queue();
+               if (retval != ERROR_OK)
                        return retval;
 
                if (buf_get_u32(field0_in, hsbit, 1) == hsact)
@@ -608,6 +626,7 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
        } while ((uint32_t)((now.tv_sec - lap.tv_sec) * 1000
                        + (now.tv_usec - lap.tv_usec) / 1000) <= timeout);
 
+       LOG_ERROR("embeddedice handshake timeout");
        return ERROR_TARGET_TIMEOUT;
 }
 
@@ -616,12 +635,11 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
  * This is an inner loop of the open loop DCC write of data to target
  */
 void embeddedice_write_dcc(struct jtag_tap *tap,
-               int reg_addr, uint8_t *buffer, int little, int count)
+               int reg_addr, const uint8_t *buffer, int little, int count)
 {
        int i;
 
-       for (i = 0; i < count; i++)
-       {
+       for (i = 0; i < count; i++) {
                embeddedice_write_reg_inner(tap, reg_addr,
                                fast_target_buffer_get_u32(buffer, little));
                buffer += 4;
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