#include "target_type.h"
#include "dsp5680xx.h"
+struct dsp5680xx_common dsp5680xx_context;
+
+
#define err_check(retval,err_msg) if(retval != ERROR_OK){LOG_ERROR("%s: %d %s.",__FUNCTION__,__LINE__,err_msg);return retval;}
#define err_check_propagate(retval) if(retval!=ERROR_OK){return retval;}
//can i send as many bits as i want?
//is the casting necessary?
jtag_add_plain_dr_scan(len,data_to_shift_into_dr,data_shifted_out_of_dr, TAP_IDLE);
- if(context.flush){
+ if(dsp5680xx_context.flush){
retval = dsp5680xx_execute_queue();
err_check_propagate(retval);
}
//can i send as many bits as i want?
//is the casting necessary?
jtag_add_plain_ir_scan(ir_len,(uint8_t *)data_to_shift_into_ir,(uint8_t *)data_shifted_out_of_ir, TAP_IDLE);
- if(context.flush){
+ if(dsp5680xx_context.flush){
retval = dsp5680xx_execute_queue();
err_check_propagate(retval);
}
return ERROR_OK;
}
-static int jtag_data_read(struct target * target, uint32_t * data_read, int num_bits){
- uint32_t bogus_instr;
- int retval = dsp5680xx_drscan(target,(uint8_t *) & bogus_instr,(uint8_t *) data_read,num_bits);
+static int jtag_data_read(struct target * target, uint8_t * data_read, int num_bits){
+ uint32_t bogus_instr = 0;
+ int retval = dsp5680xx_drscan(target,(uint8_t *) & bogus_instr,data_read,num_bits);
LOG_DEBUG("Data read (%d bits): 0x%04X",num_bits,*data_read);//TODO remove this or move to jtagio?
return retval;
}
#define jtag_data_read16(target,data_read) jtag_data_read(target,data_read,16)
#define jtag_data_read32(target,data_read) jtag_data_read(target,data_read,32)
+static uint32_t data_read_dummy;
static int jtag_data_write(struct target * target, uint32_t instr,int num_bits, uint32_t * data_read){
int retval;
- uint32_t data_read_dummy;
retval = dsp5680xx_drscan(target,(uint8_t *) & instr,(uint8_t *) & data_read_dummy,num_bits);
err_check_propagate(retval);
if(data_read != NULL)
#define jtag_data_write32(target,instr,data_read) jtag_data_write(target,instr,32,data_read)
/**
- * Executes DSP instruction.
+ * Executes EOnCE instruction.
*
* @param target
* @param instr Instruction to execute.
*
* @return
*/
-
-static int eonce_instruction_exec(struct target * target, uint8_t instr, uint8_t rw, uint8_t go, uint8_t ex,uint8_t * eonce_status){
+static int eonce_instruction_exec_single(struct target * target, uint8_t instr, uint8_t rw, uint8_t go, uint8_t ex,uint8_t * eonce_status){
int retval;
uint32_t dr_out_tmp;
uint8_t instr_with_flags = instr|(rw<<7)|(go<<6)|(ex<<5);
return retval;
}
-///wrappers for parameter conversion between eonce_execute_instruction and eonce_execute_instructionX
-
-#define eonce_execute_instruction_1(target,opcode1,opcode2,opcode3) eonce_execute_instruction1(target,opcode1)
-#define eonce_execute_instruction_2(target,opcode1,opcode2,opcode3) eonce_execute_instruction2(target,opcode1,opcode2)
-#define eonce_execute_instruction_3(target,opcode1,opcode2,opcode3) eonce_execute_instruction3(target,opcode1,opcode2,opcode3)
-#define eonce_execute_instruction(target,words,opcode1,opcode2,opcode3) eonce_execute_instruction_##words(target,opcode1,opcode2,opcode3)
+///wrappers for multi opcode instructions
+#define dsp5680xx_exe_1(target,opcode1,opcode2,opcode3) dsp5680xx_exe1(target,opcode1)
+#define dsp5680xx_exe_2(target,opcode1,opcode2,opcode3) dsp5680xx_exe2(target,opcode1,opcode2)
+#define dsp5680xx_exe_3(target,opcode1,opcode2,opcode3) dsp5680xx_exe3(target,opcode1,opcode2,opcode3)
+#define dsp5680xx_exe_generic(target,words,opcode1,opcode2,opcode3) dsp5680xx_exe_##words(target,opcode1,opcode2,opcode3)
/// Executes one word DSP instruction
-static int eonce_execute_instruction1(struct target * target, uint16_t opcode){
+static int dsp5680xx_exe1(struct target * target, uint16_t opcode){
int retval;
- retval = eonce_instruction_exec(target,0x04,0,1,0,NULL);
+ retval = eonce_instruction_exec_single(target,0x04,0,1,0,NULL);
err_check_propagate(retval);
retval = jtag_data_write16(target,opcode,NULL);
err_check_propagate(retval);
}
/// Executes two word DSP instruction
-static int eonce_execute_instruction2(struct target * target,uint16_t opcode1, uint16_t opcode2){
+static int dsp5680xx_exe2(struct target * target,uint16_t opcode1, uint16_t opcode2){
int retval;
- retval = eonce_instruction_exec(target,0x04,0,0,0,NULL);
+ retval = eonce_instruction_exec_single(target,0x04,0,0,0,NULL);
err_check_propagate(retval);
retval = jtag_data_write16(target,opcode1,NULL);
err_check_propagate(retval);
- retval = eonce_instruction_exec(target,0x04,0,1,0,NULL);
+ retval = eonce_instruction_exec_single(target,0x04,0,1,0,NULL);
err_check_propagate(retval);
retval = jtag_data_write16(target,opcode2,NULL);
err_check_propagate(retval);
}
/// Executes three word DSP instruction
-static int eonce_execute_instruction3(struct target * target, uint16_t opcode1,uint16_t opcode2,uint16_t opcode3){
+static int dsp5680xx_exe3(struct target * target, uint16_t opcode1,uint16_t opcode2,uint16_t opcode3){
int retval;
- retval = eonce_instruction_exec(target,0x04,0,0,0,NULL);
+ retval = eonce_instruction_exec_single(target,0x04,0,0,0,NULL);
err_check_propagate(retval);
retval = jtag_data_write16(target,opcode1,NULL);
err_check_propagate(retval);
- retval = eonce_instruction_exec(target,0x04,0,0,0,NULL);
+ retval = eonce_instruction_exec_single(target,0x04,0,0,0,NULL);
err_check_propagate(retval);
retval = jtag_data_write16(target,opcode2,NULL);
err_check_propagate(retval);
- retval = eonce_instruction_exec(target,0x04,0,1,0,NULL);
+ retval = eonce_instruction_exec_single(target,0x04,0,1,0,NULL);
err_check_propagate(retval);
retval = jtag_data_write16(target,opcode3,NULL);
err_check_propagate(retval);
*/
/// writes data into upper ORx register of the target
-static int eonce_tx_upper_data(struct target * target, uint16_t data, uint32_t * eonce_status_low){
+static int core_tx_upper_data(struct target * target, uint16_t data, uint32_t * eonce_status_low){
int retval;
- retval = eonce_instruction_exec(target,DSP5680XX_ONCE_ORX1,0,0,0,NULL);
+ retval = eonce_instruction_exec_single(target,DSP5680XX_ONCE_ORX1,0,0,0,NULL);
err_check_propagate(retval);
retval = jtag_data_write16(target,data,eonce_status_low);
err_check_propagate(retval);
}
/// writes data into lower ORx register of the target
-#define eonce_tx_lower_data(target,data) eonce_instruction_exec(target,DSP5680XX_ONCE_ORX,0,0,0,NULL);\
+#define core_tx_lower_data(target,data) eonce_instruction_exec_single(target,DSP5680XX_ONCE_ORX,0,0,0,NULL);\
jtag_data_write16(target,data)
/**
* @param data_read: Returns the data read from the upper OTX register via JTAG.
* @return: Returns an error code (see error code documentation)
*/
-static int eonce_rx_upper_data(struct target * target, uint16_t * data_read)
+static int core_rx_upper_data(struct target * target, uint8_t * data_read)
{
int retval;
- retval = eonce_instruction_exec(target,DSP5680XX_ONCE_OTX1,1,0,0,NULL);
+ retval = eonce_instruction_exec_single(target,DSP5680XX_ONCE_OTX1,1,0,0,NULL);
err_check_propagate(retval);
- retval = jtag_data_read16(target,(uint32_t *)data_read);
+ retval = jtag_data_read16(target,data_read);
err_check_propagate(retval);
return retval;
}
* @param data_read: Returns the data read from the lower OTX register via JTAG.
* @return: Returns an error code (see error code documentation)
*/
-static int eonce_rx_lower_data(struct target * target,uint16_t * data_read)
+static int core_rx_lower_data(struct target * target,uint8_t * data_read)
{
int retval;
- retval = eonce_instruction_exec(target,DSP5680XX_ONCE_OTX,1,0,0,NULL);
+ retval = eonce_instruction_exec_single(target,DSP5680XX_ONCE_OTX,1,0,0,NULL);
err_check_propagate(retval);
- retval = jtag_data_read16(target,(uint32_t *)data_read);
+ retval = jtag_data_read16(target,data_read);
err_check_propagate(retval);
return retval;
}
*/
/// move.l #value,r0
-#define eonce_move_long_to_r0(target,value) eonce_execute_instruction(target,3,0xe418,value&0xffff,value>>16)
+#define core_move_long_to_r0(target,value) dsp5680xx_exe_generic(target,3,0xe418,value&0xffff,value>>16)
/// move.l #value,n
-#define eonce_move_long_to_n(target,value) eonce_execute_instruction(target,3,0xe41e,value&0xffff,value>>16)
+#define core_move_long_to_n(target,value) dsp5680xx_exe_generic(target,3,0xe41e,value&0xffff,value>>16)
/// move x:(r0),y0
-#define eonce_move_at_r0_to_y0(target) eonce_execute_instruction(target,1,0xF514,0,0)
+#define core_move_at_r0_to_y0(target) dsp5680xx_exe_generic(target,1,0xF514,0,0)
/// move x:(r0),y1
-#define eonce_move_at_r0_to_y1(target) eonce_execute_instruction(target,1,0xF714,0,0)
+#define core_move_at_r0_to_y1(target) dsp5680xx_exe_generic(target,1,0xF714,0,0)
/// move.l x:(r0),y
-#define eonce_move_long_at_r0_y(target) eonce_execute_instruction(target,1,0xF734,0,0)
+#define core_move_long_at_r0_y(target) dsp5680xx_exe_generic(target,1,0xF734,0,0)
/// move y0,x:(r0)
-#define eonce_move_y0_at_r0(target) eonce_execute_instruction(target,1,0xd514,0,0)
+#define core_move_y0_at_r0(target) dsp5680xx_exe_generic(target,1,0xd514,0,0)
/// bfclr #value,x:(r0)
-#define eonce_bfclr_at_r0(target,value) eonce_execute_instruction(target,2,0x8040,value,0)
+#define eonce_bfclr_at_r0(target,value) dsp5680xx_exe_generic(target,2,0x8040,value,0)
/// move #value,y0
-#define eonce_move_value_to_y0(target,value) eonce_execute_instruction(target,2,0x8745,value,0)
+#define core_move_value_to_y0(target,value) dsp5680xx_exe_generic(target,2,0x8745,value,0)
/// move.w y0,x:(r0)+
-#define eonce_move_y0_at_r0_inc(target) eonce_execute_instruction(target,1,0xd500,0,0)
+#define core_move_y0_at_r0_inc(target) dsp5680xx_exe_generic(target,1,0xd500,0,0)
/// move.w y0,p:(r0)+
-#define eonce_move_y0_at_pr0_inc(target) eonce_execute_instruction(target,1,0x8560,0,0)
+#define core_move_y0_at_pr0_inc(target) dsp5680xx_exe_generic(target,1,0x8560,0,0)
/// move.w p:(r0)+,y0
-#define eonce_move_at_pr0_inc_to_y0(target) eonce_execute_instruction(target,1,0x8568,0,0)
+#define core_move_at_pr0_inc_to_y0(target) dsp5680xx_exe_generic(target,1,0x8568,0,0)
/// move.w p:(r0)+,y1
-#define eonce_move_at_pr0_inc_to_y1(target) eonce_execute_instruction(target,1,0x8768,0,0)
+#define core_move_at_pr0_inc_to_y1(target) dsp5680xx_exe_generic(target,1,0x8768,0,0)
/// move.l #value,r2
-#define eonce_move_long_to_r2(target,value) eonce_execute_instruction(target,3,0xe41A,value&0xffff,value>>16)
+#define core_move_long_to_r2(target,value) dsp5680xx_exe_generic(target,3,0xe41A,value&0xffff,value>>16)
/// move y0,x:(r2)
-#define eonce_move_y0_at_r2(target) eonce_execute_instruction(target,1,0xd516,0,0)
+#define core_move_y0_at_r2(target) dsp5680xx_exe_generic(target,1,0xd516,0,0)
/// move.w #<value>,x:(r2)
-#define eonce_move_value_at_r2(target,value) eonce_execute_instruction(target,2,0x8642,value,0)
+#define core_move_value_at_r2(target,value) dsp5680xx_exe_generic(target,2,0x8642,value,0)
/// move.w #<value>,x:(r0)
-#define eonce_move_value_at_r0(target,value) eonce_execute_instruction(target,2,0x8640,value,0)
+#define core_move_value_at_r0(target,value) dsp5680xx_exe_generic(target,2,0x8640,value,0)
/// move.w #<value>,x:(R2+<disp>)
-#define eonce_move_value_at_r2_disp(target,value,disp) eonce_execute_instruction(target,3,0x8646,value,disp)
+#define core_move_value_at_r2_disp(target,value,disp) dsp5680xx_exe_generic(target,3,0x8646,value,disp)
/// move.w x:(r2),Y0
-#define eonce_move_at_r2_to_y0(target) eonce_execute_instruction(target,1,0xF516,0,0)
+#define core_move_at_r2_to_y0(target) dsp5680xx_exe_generic(target,1,0xF516,0,0)
/// move.w p:(r2)+,y0
-#define eonce_move_at_pr2_inc_to_y0(target) eonce_execute_instruction(target,1,0x856A,0,0)
+#define core_move_at_pr2_inc_to_y0(target) dsp5680xx_exe_generic(target,1,0x856A,0,0)
/// move.l #value,r3
-#define eonce_move_long_to_r1(target,value) eonce_execute_instruction(target,3,0xE419,value&0xffff,value>>16)
+#define core_move_long_to_r1(target,value) dsp5680xx_exe_generic(target,3,0xE419,value&0xffff,value>>16)
/// move.l #value,r3
-#define eonce_move_long_to_r3(target,value) eonce_execute_instruction(target,3,0xE41B,value&0xffff,value>>16)
+#define core_move_long_to_r3(target,value) dsp5680xx_exe_generic(target,3,0xE41B,value&0xffff,value>>16)
/// move.w y0,p:(r3)+
-#define eonce_move_y0_at_pr3_inc(target) eonce_execute_instruction(target,1,0x8563,0,0)
+#define core_move_y0_at_pr3_inc(target) dsp5680xx_exe_generic(target,1,0x8563,0,0)
/// move.w y0,x:(r3)
-#define eonce_move_y0_at_r3(target) eonce_execute_instruction(target,1,0xD503,0,0)
+#define core_move_y0_at_r3(target) dsp5680xx_exe_generic(target,1,0xD503,0,0)
/// move.l #value,r4
-#define eonce_move_long_to_r4(target,value) eonce_execute_instruction(target,3,0xE41C,value&0xffff,value>>16)
+#define core_move_long_to_r4(target,value) dsp5680xx_exe_generic(target,3,0xE41C,value&0xffff,value>>16)
/// move pc,r4
-#define eonce_move_pc_to_r4(target) eonce_execute_instruction(target,1,0xE716,0,0)
+#define core_move_pc_to_r4(target) dsp5680xx_exe_generic(target,1,0xE716,0,0)
/// move.l r4,y
-#define eonce_move_r4_to_y(target) eonce_execute_instruction(target,1,0xe764,0,0)
+#define core_move_r4_to_y(target) dsp5680xx_exe_generic(target,1,0xe764,0,0)
/// move.w p:(r0)+,y0
-#define eonce_move_at_pr0_inc_to_y0(target) eonce_execute_instruction(target,1,0x8568,0,0)
+#define core_move_at_pr0_inc_to_y0(target) dsp5680xx_exe_generic(target,1,0x8568,0,0)
/// move.w x:(r0)+,y0
-#define eonce_move_at_r0_inc_to_y0(target) eonce_execute_instruction(target,1,0xf500,0,0)
+#define core_move_at_r0_inc_to_y0(target) dsp5680xx_exe_generic(target,1,0xf500,0,0)
/// move x:(r0),y0
-#define eonce_move_at_r0_y0(target) eonce_execute_instruction(target,1,0xF514,0,0)
+#define core_move_at_r0_y0(target) dsp5680xx_exe_generic(target,1,0xF514,0,0)
/// nop
-#define eonce_nop(target) eonce_execute_instruction(target,1,0xe700,0,0)
+#define eonce_nop(target) dsp5680xx_exe_generic(target,1,0xe700,0,0)
/// move.w x:(R2+<disp>),Y0
-#define eonce_move_at_r2_disp_to_y0(target,disp) eonce_execute_instruction(target,2,0xF542,disp,0)
+#define core_move_at_r2_disp_to_y0(target,disp) dsp5680xx_exe_generic(target,2,0xF542,disp,0)
/// move.w y1,x:(r2)
-#define eonce_move_y1_at_r2(target) eonce_execute_instruction(target,1,0xd716,0,0)
+#define core_move_y1_at_r2(target) dsp5680xx_exe_generic(target,1,0xd716,0,0)
/// move.w y1,x:(r0)
-#define eonce_move_y1_at_r0(target) eonce_execute_instruction(target,1,0xd714,0,0)
+#define core_move_y1_at_r0(target) dsp5680xx_exe_generic(target,1,0xd714,0,0)
/// move.bp y0,x:(r0)+
-#define eonce_move_byte_y0_at_r0(target) eonce_execute_instruction(target,1,0xd5a0,0,0)
+#define core_move_byte_y0_at_r0(target) dsp5680xx_exe_generic(target,1,0xd5a0,0,0)
/// move.w y1,p:(r0)+
-#define eonce_move_y1_at_pr0_inc(target) eonce_execute_instruction(target,1,0x8760,0,0)
+#define core_move_y1_at_pr0_inc(target) dsp5680xx_exe_generic(target,1,0x8760,0,0)
/// move.w y1,x:(r0)+
-#define eonce_move_y1_at_r0_inc(target) eonce_execute_instruction(target,1,0xD700,0,0)
+#define core_move_y1_at_r0_inc(target) dsp5680xx_exe_generic(target,1,0xD700,0,0)
/// move.l #value,y
-#define eonce_move_long_to_y(target,value) eonce_execute_instruction(target,3,0xe417,value&0xffff,value>>16)
+#define core_move_long_to_y(target,value) dsp5680xx_exe_generic(target,3,0xe417,value&0xffff,value>>16)
-static int eonce_move_value_to_pc(struct target * target, uint32_t value){
+static int core_move_value_to_pc(struct target * target, uint32_t value){
if (!(target->state == TARGET_HALTED)){
LOG_ERROR("Target must be halted to move PC. Target state = %d.",target->state);
return ERROR_TARGET_NOT_HALTED;
};
int retval;
- retval = eonce_execute_instruction(target,3,0xE71E,value&0xffff,value>>16);
+ retval = dsp5680xx_exe_generic(target,3,0xE71E,value&0xffff,value>>16);
err_check_propagate(retval);
return retval;
}
static int eonce_load_TX_RX_to_r0(struct target * target)
{
int retval;
- retval = eonce_move_long_to_r0(target,((MC568013_EONCE_TX_RX_ADDR)+(MC568013_EONCE_OBASE_ADDR<<16)));
+ retval = core_move_long_to_r0(target,((MC568013_EONCE_TX_RX_ADDR)+(MC568013_EONCE_OBASE_ADDR<<16)));
return retval;
}
-static int eonce_load_TX_RX_high_to_r0(struct target * target)
+static int core_load_TX_RX_high_addr_to_r0(struct target * target)
{
int retval = 0;
- retval = eonce_move_long_to_r0(target,((MC568013_EONCE_TX1_RX1_HIGH_ADDR)+(MC568013_EONCE_OBASE_ADDR<<16)));
+ retval = core_move_long_to_r0(target,((MC568013_EONCE_TX1_RX1_HIGH_ADDR)+(MC568013_EONCE_OBASE_ADDR<<16)));
return retval;
}
//TODO implement a general version of this which matches what openocd uses.
int retval;
uint32_t dummy_data_to_shift_into_dr;
- retval = eonce_instruction_exec(target,reg_addr,1,0,0,NULL);
+ retval = eonce_instruction_exec_single(target,reg_addr,1,0,0,NULL);
err_check_propagate(retval);
retval = dsp5680xx_drscan(target,(uint8_t *)& dummy_data_to_shift_into_dr,(uint8_t *) data_read, 8);
err_check_propagate(retval);
*/
static int eonce_exit_debug_mode(struct target * target,uint8_t * eonce_status){
int retval;
- retval = eonce_instruction_exec(target,0x1F,0,0,1,eonce_status);
+ retval = eonce_instruction_exec_single(target,0x1F,0,0,1,eonce_status);
err_check_propagate(retval);
return retval;
}
+int switch_tap(struct target * target, struct jtag_tap * master_tap,struct jtag_tap * core_tap){
+ int retval = ERROR_OK;
+ uint32_t instr;
+ uint32_t ir_out;//not used, just to make jtag happy.
+ if(master_tap == NULL){
+ master_tap = jtag_tap_by_string("dsp568013.chp");
+ if(master_tap == NULL){
+ retval = ERROR_FAIL;
+ err_check(retval,"Failed to get master tap.");
+ }
+ }
+ if(core_tap == NULL){
+ core_tap = jtag_tap_by_string("dsp568013.cpu");
+ if(core_tap == NULL){
+ retval = ERROR_FAIL;
+ err_check(retval,"Failed to get core tap.");
+ }
+ }
+
+ if(!(((int)master_tap->enabled) ^ ((int)core_tap->enabled))){
+ LOG_WARNING("Wrong tap enabled/disabled status:\nMaster tap:%d\nCore Tap:%d\nOnly one tap should be enabled at a given time.\n",(int)master_tap->enabled,(int)core_tap->enabled);
+ }
+
+ if(master_tap->enabled){
+ instr = 0x5;
+ retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_MASTER_TAP_IRLEN);
+ err_check_propagate(retval);
+ instr = 0x2;
+ retval = dsp5680xx_drscan(target,(uint8_t *) & instr,(uint8_t *) & ir_out,4);
+ err_check_propagate(retval);
+ core_tap->enabled = true;
+ master_tap->enabled = false;
+ }else{
+ instr = 0x08;
+ retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
+ err_check_propagate(retval);
+ instr = 0x1;
+ retval = dsp5680xx_drscan(target,(uint8_t *) & instr,(uint8_t *) & ir_out,4);
+ err_check_propagate(retval);
+ core_tap->enabled = false;
+ master_tap->enabled = true;
+ }
+ return retval;
+}
+
+#define TIME_DIV_FREESCALE 0.3
/**
* Puts the core into debug mode, enabling the EOnCE module.
*
* @return
*/
static int eonce_enter_debug_mode(struct target * target, uint16_t * eonce_status){
- int retval;
+ int retval = ERROR_OK;
uint32_t instr = JTAG_INSTR_DEBUG_REQUEST;
uint32_t ir_out;//not used, just to make jtag happy.
- // Debug request #1
- retval = dsp5680xx_irscan(target,& instr,& ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
+ uint16_t instr_16;
+ uint16_t read_16;
+
+ struct jtag_tap * tap_chp;
+ struct jtag_tap * tap_cpu;
+ tap_chp = jtag_tap_by_string("dsp568013.chp");
+ if(tap_chp == NULL){
+ retval = ERROR_FAIL;
+ err_check(retval,"Failed to get master tap.");
+ }
+ tap_cpu = jtag_tap_by_string("dsp568013.cpu");
+ if(tap_cpu == NULL){
+ retval = ERROR_FAIL;
+ err_check(retval,"Failed to get master tap.");
+ }
+
+ tap_chp->enabled = false;
+ retval = switch_tap(target,tap_chp,tap_cpu);
+ err_check_propagate(retval);
+
+ instr = MASTER_TAP_CMD_IDCODE;
+ retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_MASTER_TAP_IRLEN);
err_check_propagate(retval);
+ usleep(TIME_DIV_FREESCALE*100*1000);
// Enable EOnCE module
+ jtag_add_reset(0,1);
+ usleep(TIME_DIV_FREESCALE*200*1000);
+ instr = 0x0606ffff;// This was selected experimentally.
+ retval = dsp5680xx_drscan(target,(uint8_t *) & instr,(uint8_t *) & ir_out,32);
+ err_check_propagate(retval);
+ // ir_out now hold tap idcode
+
+ // Enable core tap
+ retval = switch_tap(target,tap_chp,tap_cpu);
+ err_check_propagate(retval);
+
instr = JTAG_INSTR_ENABLE_ONCE;
//Two rounds of jtag 0x6 (enable eonce) to enable EOnCE.
retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
err_check_propagate(retval);
+ instr = JTAG_INSTR_DEBUG_REQUEST;
retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
err_check_propagate(retval);
+ instr_16 = 0x1;
+ retval = dsp5680xx_drscan(target,(uint8_t *) & instr_16,(uint8_t *) & read_16,8);
+ instr_16 = 0x20;
+ retval = dsp5680xx_drscan(target,(uint8_t *) & instr_16,(uint8_t *) & read_16,8);
+ usleep(TIME_DIV_FREESCALE*100*1000);
+ jtag_add_reset(0,0);
+ usleep(TIME_DIV_FREESCALE*300*1000);
+
+ instr = JTAG_INSTR_ENABLE_ONCE;
+ //Two rounds of jtag 0x6 (enable eonce) to enable EOnCE.
+ for(int i = 0; i<3; i++){
+ retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
+ err_check_propagate(retval);
+ }
+
+ for(int i = 0; i<3; i++){
+ instr_16 = 0x86;
+ dsp5680xx_drscan(target,(uint8_t *) & instr_16,(uint8_t *) & read_16,16);
+ instr_16 = 0xff;
+ dsp5680xx_drscan(target,(uint8_t *) & instr_16,(uint8_t *) & read_16,16);
+ }
+
// Verify that debug mode is enabled
uint16_t data_read_from_dr;
retval = eonce_read_status_reg(target,&data_read_from_dr);
if((data_read_from_dr&0x30) == 0x30){
LOG_DEBUG("EOnCE successfully entered debug mode.");
target->state = TARGET_HALTED;
- return ERROR_OK;
+ retval = ERROR_OK;
}else{
+ LOG_DEBUG("Failed to set EOnCE module to debug mode.");
retval = ERROR_TARGET_FAILURE;
- err_check(retval,"Failed to set EOnCE module to debug mode.");
}
if(eonce_status!=NULL)
*eonce_status = data_read_from_dr;
- return ERROR_OK;
+ return retval;
}
/**
* @return
*/
static int eonce_pc_store(struct target * target){
- uint32_t tmp = 0;
+ uint8_t tmp[2];
int retval;
- retval = eonce_move_pc_to_r4(target);
+ retval = core_move_pc_to_r4(target);
err_check_propagate(retval);
- retval = eonce_move_r4_to_y(target);
+ retval = core_move_r4_to_y(target);
err_check_propagate(retval);
retval = eonce_load_TX_RX_to_r0(target);
err_check_propagate(retval);
- retval = eonce_move_y0_at_r0(target);
+ retval = core_move_y0_at_r0(target);
err_check_propagate(retval);
- retval = eonce_rx_lower_data(target,(uint16_t *)&tmp);
+ retval = core_rx_lower_data(target,tmp);
err_check_propagate(retval);
- LOG_USER("PC value: 0x%06X\n",tmp);
- context.stored_pc = (uint32_t)tmp;
+ LOG_USER("PC value: 0x%X%X\n",tmp[1],tmp[0]);
+ dsp5680xx_context.stored_pc = (tmp[0]|(tmp[1]<<8));
return ERROR_OK;
}
}
static int dsp5680xx_init_target(struct command_context *cmd_ctx, struct target *target){
- context.stored_pc = 0;
- context.flush = 1;
+ dsp5680xx_context.stored_pc = 0;
+ dsp5680xx_context.flush = 1;
LOG_DEBUG("target initiated!");
//TODO core tap must be enabled before running these commands, currently this is done in the .cfg tcl script.
return ERROR_OK;
static int dsp5680xx_halt(struct target *target){
int retval;
- uint16_t eonce_status;
+ uint16_t eonce_status = 0xbeef;
if(target->state == TARGET_HALTED){
LOG_USER("Target already halted.");
return ERROR_OK;
}
retval = eonce_enter_debug_mode(target,&eonce_status);
- err_check_propagate(retval);
+ err_check(retval,"Failed to halt target.");
retval = eonce_pc_store(target);
err_check_propagate(retval);
//TODO is it useful to store the pc?
int retval;
uint8_t eonce_status;
if(!current){
- retval = eonce_move_value_to_pc(target,address);
+ retval = core_move_value_to_pc(target,address);
err_check_propagate(retval);
}
return ERROR_OK;
}
-static int dsp5680xx_read_16_single(struct target * target, uint32_t address, uint16_t * data_read, int r_pmem){
- //TODO add error control!
+static int dsp5680xx_read_16_single(struct target * target, uint32_t address, uint8_t * data_read, int r_pmem){
int retval;
- retval = eonce_move_long_to_r0(target,address);
+ retval = core_move_long_to_r0(target,address);
err_check_propagate(retval);
if(r_pmem)
- retval = eonce_move_at_pr0_inc_to_y0(target);
+ retval = core_move_at_pr0_inc_to_y0(target);
else
- retval = eonce_move_at_r0_to_y0(target);
+ retval = core_move_at_r0_to_y0(target);
err_check_propagate(retval);
retval = eonce_load_TX_RX_to_r0(target);
err_check_propagate(retval);
- retval = eonce_move_y0_at_r0(target);
+ retval = core_move_y0_at_r0(target);
err_check_propagate(retval);
// at this point the data i want is at the reg eonce can read
- retval = eonce_rx_lower_data(target,data_read);
+ retval = core_rx_lower_data(target,data_read);
err_check_propagate(retval);
- LOG_DEBUG("%s: Data read from 0x%06X: 0x%04X",__FUNCTION__, address,*data_read);
+ LOG_DEBUG("%s: Data read from 0x%06X: 0x%02X%02X",__FUNCTION__, address,data_read[1],data_read[0]);
return retval;
}
-static int dsp5680xx_read_32_single(struct target * target, uint32_t address, uint32_t * data_read, int r_pmem){
+static int dsp5680xx_read_32_single(struct target * target, uint32_t address, uint8_t * data_read, int r_pmem){
int retval;
address = (address & 0xFFFFFE);
// Get data to an intermediate register
- retval = eonce_move_long_to_r0(target,address);
+ retval = core_move_long_to_r0(target,address);
err_check_propagate(retval);
if(r_pmem){
- retval = eonce_move_at_pr0_inc_to_y0(target);
+ retval = core_move_at_pr0_inc_to_y0(target);
err_check_propagate(retval);
- retval = eonce_move_at_pr0_inc_to_y1(target);
+ retval = core_move_at_pr0_inc_to_y1(target);
err_check_propagate(retval);
}else{
- retval = eonce_move_at_r0_inc_to_y0(target);
+ retval = core_move_at_r0_inc_to_y0(target);
err_check_propagate(retval);
- retval = eonce_move_at_r0_to_y1(target);
+ retval = core_move_at_r0_to_y1(target);
err_check_propagate(retval);
}
// Get lower part of data to TX/RX
retval = eonce_load_TX_RX_to_r0(target);
err_check_propagate(retval);
- retval = eonce_move_y0_at_r0_inc(target); // This also load TX/RX high to r0
+ retval = core_move_y0_at_r0_inc(target); // This also load TX/RX high to r0
err_check_propagate(retval);
// Get upper part of data to TX/RX
- retval = eonce_move_y1_at_r0(target);
+ retval = core_move_y1_at_r0(target);
err_check_propagate(retval);
// at this point the data i want is at the reg eonce can read
- retval = eonce_rx_lower_data(target,(uint16_t * )data_read);
+ retval = core_rx_lower_data(target,data_read);
err_check_propagate(retval);
- uint16_t tmp;
- retval = eonce_rx_upper_data(target,&tmp);
+ retval = core_rx_upper_data(target,data_read+2);
err_check_propagate(retval);
- *data_read = ((tmp<<16) | (*data_read));//This enables OpenOCD crc to succeed (when it should)
return retval;
}
static int dsp5680xx_read(struct target * target, uint32_t address, unsigned size, unsigned count, uint8_t * buffer){
if(target->state != TARGET_HALTED){
LOG_USER("Target must be halted.");
- return ERROR_OK;
+ return ERROR_FAIL;
}
- uint32_t * buff32 = (uint32_t *) buffer;
- uint16_t * buff16 = (uint16_t *) buffer;
int retval = ERROR_OK;
int pmem = 1;
- uint16_t tmp_wrd;
retval = dsp5680xx_convert_address(&address, &pmem);
err_check_propagate(retval);
- context.flush = 0;
+ dsp5680xx_context.flush = 0;
int counter = FLUSH_COUNT_READ_WRITE;
for (unsigned i=0; i<count; i++){
if(--counter==0){
- context.flush = 1;
- counter = FLUSH_COUNT_FLASH;
+ dsp5680xx_context.flush = 1;
+ counter = FLUSH_COUNT_READ_WRITE;
}
switch (size){
case 1:
if(!(i%2)){
- retval = dsp5680xx_read_16_single(target, address + i/2, &tmp_wrd, pmem);
- buffer[i] = (uint8_t) (tmp_wrd>>8);
- buffer[i+1] = (uint8_t) (tmp_wrd&0xff);
+ retval = dsp5680xx_read_16_single(target, address + i/2, buffer + i, pmem);
}
break;
case 2:
- retval = dsp5680xx_read_16_single(target, address + i, buff16 + i, pmem);
+ retval = dsp5680xx_read_16_single(target, address + i, buffer+2*i, pmem);
break;
case 4:
- retval = dsp5680xx_read_32_single(target, address + 2*i, buff32 + i, pmem);
+ retval = dsp5680xx_read_32_single(target, address + 2*i, buffer + 4*i, pmem);
break;
default:
LOG_USER("%s: Invalid read size.",__FUNCTION__);
break;
}
err_check_propagate(retval);
- context.flush = 0;
+ dsp5680xx_context.flush = 0;
}
- context.flush = 1;
+ dsp5680xx_context.flush = 1;
retval = dsp5680xx_execute_queue();
err_check_propagate(retval);
static int dsp5680xx_write_16_single(struct target *target, uint32_t address, uint16_t data, uint8_t w_pmem){
int retval = 0;
- retval = eonce_move_long_to_r0(target,address);
+ retval = core_move_long_to_r0(target,address);
err_check_propagate(retval);
if(w_pmem){
- retval = eonce_move_value_to_y0(target,data);
+ retval = core_move_value_to_y0(target,data);
err_check_propagate(retval);
- retval = eonce_move_y0_at_pr0_inc(target);
+ retval = core_move_y0_at_pr0_inc(target);
err_check_propagate(retval);
}else{
- retval = eonce_move_value_at_r0(target,data);
+ retval = core_move_value_at_r0(target,data);
err_check_propagate(retval);
}
return retval;
static int dsp5680xx_write_32_single(struct target *target, uint32_t address, uint32_t data, int w_pmem){
int retval = 0;
- retval = eonce_move_long_to_r0(target,address);
+ retval = core_move_long_to_r0(target,address);
err_check_propagate(retval);
- retval = eonce_move_long_to_y(target,data);
+ retval = core_move_long_to_y(target,data);
err_check_propagate(retval);
if(w_pmem)
- retval = eonce_move_y0_at_pr0_inc(target);
+ retval = core_move_y0_at_pr0_inc(target);
else
- retval = eonce_move_y0_at_r0_inc(target);
+ retval = core_move_y0_at_r0_inc(target);
err_check_propagate(retval);
if(w_pmem)
- retval = eonce_move_y1_at_pr0_inc(target);
+ retval = core_move_y1_at_pr0_inc(target);
else
- retval = eonce_move_y1_at_r0_inc(target);
+ retval = core_move_y1_at_r0_inc(target);
err_check_propagate(retval);
return retval;
}
-static int dsp5680xx_write_8(struct target * target, uint32_t address, uint32_t count, uint8_t * data, int pmem){
+static int dsp5680xx_write_8(struct target * target, uint32_t address, uint32_t count, const uint8_t * data, int pmem){
if(target->state != TARGET_HALTED){
LOG_ERROR("%s: Target must be halted.",__FUNCTION__);
return ERROR_OK;
};
int retval = 0;
- uint16_t * data_w = (uint16_t *)data;
+ uint16_t data_16;
uint32_t iter;
int counter = FLUSH_COUNT_READ_WRITE;
for(iter = 0; iter<count/2; iter++){
if(--counter==0){
- context.flush = 1;
+ dsp5680xx_context.flush = 1;
counter = FLUSH_COUNT_READ_WRITE;
}
- retval = dsp5680xx_write_16_single(target,address+iter,data_w[iter], pmem);
+ data_16=(data[2*iter]|(data[2*iter+1]<<8));
+ retval = dsp5680xx_write_16_single(target,address+iter,data_16, pmem);
if(retval != ERROR_OK){
LOG_ERROR("%s: Could not write to p:0x%04X",__FUNCTION__,address);
- context.flush = 1;
+ dsp5680xx_context.flush = 1;
return retval;
}
- context.flush = 0;
+ dsp5680xx_context.flush = 0;
}
- context.flush = 1;
+ dsp5680xx_context.flush = 1;
// Only one byte left, let's not overwrite the other byte (mem is 16bit)
// Need to retrieve the part we do not want to overwrite.
return retval;
}
-static int dsp5680xx_write_16(struct target * target, uint32_t address, uint32_t count, uint16_t * data, int pmem){
+static int dsp5680xx_write_16(struct target * target, uint32_t address, uint32_t count, const uint8_t * data, int pmem){
int retval = ERROR_OK;
if(target->state != TARGET_HALTED){
retval = ERROR_TARGET_NOT_HALTED;
for(iter = 0; iter<count; iter++){
if(--counter==0){
- context.flush = 1;
+ dsp5680xx_context.flush = 1;
counter = FLUSH_COUNT_READ_WRITE;
}
retval = dsp5680xx_write_16_single(target,address+iter,data[iter], pmem);
if(retval != ERROR_OK){
LOG_ERROR("%s: Could not write to p:0x%04X",__FUNCTION__,address);
- context.flush = 1;
+ dsp5680xx_context.flush = 1;
return retval;
}
- context.flush = 0;
+ dsp5680xx_context.flush = 0;
}
- context.flush = 1;
+ dsp5680xx_context.flush = 1;
return retval;
}
-static int dsp5680xx_write_32(struct target * target, uint32_t address, uint32_t count, uint32_t * data, int pmem){
+static int dsp5680xx_write_32(struct target * target, uint32_t address, uint32_t count, const uint8_t * data, int pmem){
int retval = ERROR_OK;
if(target->state != TARGET_HALTED){
retval = ERROR_TARGET_NOT_HALTED;
for(iter = 0; iter<count; iter++){
if(--counter==0){
- context.flush = 1;
+ dsp5680xx_context.flush = 1;
counter = FLUSH_COUNT_READ_WRITE;
}
retval = dsp5680xx_write_32_single(target,address+(iter<<1),data[iter], pmem);
if(retval != ERROR_OK){
LOG_ERROR("%s: Could not write to p:0x%04X",__FUNCTION__,address);
- context.flush = 1;
+ dsp5680xx_context.flush = 1;
return retval;
}
- context.flush = 0;
+ dsp5680xx_context.flush = 0;
}
- context.flush = 1;
+ dsp5680xx_context.flush = 1;
return retval;
}
switch (size){
case 1:
- retval = dsp5680xx_write_8(target, address, count,(uint8_t *) buffer, p_mem);
+ retval = dsp5680xx_write_8(target, address, count, buffer, p_mem);
break;
case 2:
- retval = dsp5680xx_write_16(target, address, count, (uint16_t *)buffer, p_mem);
+ retval = dsp5680xx_write_16(target, address, count, buffer, p_mem);
break;
case 4:
- retval = dsp5680xx_write_32(target, address, count, (uint32_t *)buffer, p_mem);
+ retval = dsp5680xx_write_32(target, address, count, buffer, p_mem);
break;
default:
retval = ERROR_TARGET_DATA_ABORT;
*
* @return
*/
-static int perl_crc(uint16_t * buff16,uint32_t word_count){
+static int perl_crc(uint8_t * buff8,uint32_t word_count){
uint16_t checksum = 0xffff;
uint16_t data,fbmisr;
uint32_t i;
for(i=0;i<word_count;i++){
- data = buff16[i];
+ data = (buff8[2*i]|(buff8[2*i+1]<<8));
fbmisr = (checksum & 2)>>1 ^ (checksum & 4)>>2 ^ (checksum & 16)>>4 ^ (checksum & 0x8000)>>15;
checksum = (data ^ ((checksum << 1) | fbmisr));
}
i--;
for(;!(i&0x80000000);i--){
- data = buff16[i];
+ data = (buff8[2*i]|(buff8[2*i+1]<<8));
fbmisr = (checksum & 2)>>1 ^ (checksum & 4)>>2 ^ (checksum & 16)>>4 ^ (checksum & 0x8000)>>15;
checksum = (data ^ ((checksum << 1) | fbmisr));
}
}
int dsp5680xx_f_protect_check(struct target * target, uint16_t * protected) {
- uint16_t aux;
int retval;
if (dsp5680xx_target_status(target,NULL,NULL) != TARGET_HALTED){
retval = dsp5680xx_halt(target);
if(protected == NULL){
err_check(ERROR_FAIL,"NULL pointer not valid.");
}
- retval = dsp5680xx_read_16_single(target,HFM_BASE_ADDR|HFM_PROT,&aux,0);
+ retval = dsp5680xx_read_16_single(target,HFM_BASE_ADDR|HFM_PROT,(uint8_t *)protected,0);
err_check_propagate(retval);
- *protected = aux;
return retval;
}
*/
static int dsp5680xx_f_execute_command(struct target * target, uint16_t command, uint32_t address, uint32_t data, uint16_t * hfm_ustat, int pmem){
int retval;
- retval = eonce_load_TX_RX_high_to_r0(target);
+ retval = core_load_TX_RX_high_addr_to_r0(target);
err_check_propagate(retval);
- retval = eonce_move_long_to_r2(target,HFM_BASE_ADDR);
+ retval = core_move_long_to_r2(target,HFM_BASE_ADDR);
err_check_propagate(retval);
- uint16_t i;
+ uint8_t i[2];
int watchdog = 100;
do{
- retval = eonce_move_at_r2_disp_to_y0(target,HFM_USTAT); // read HMF_USTAT
+ retval = core_move_at_r2_disp_to_y0(target,HFM_USTAT); // read HMF_USTAT
err_check_propagate(retval);
- retval = eonce_move_y0_at_r0(target);
+ retval = core_move_y0_at_r0(target);
err_check_propagate(retval);
- retval = eonce_rx_upper_data(target,&i);
+ retval = core_rx_upper_data(target,i);
err_check_propagate(retval);
if((watchdog--)==1){
retval = ERROR_TARGET_FAILURE;
err_check(retval,"FM execute command failed.");
}
- }while (!(i&0x40)); // wait until current command is complete
+ }while (!(i[0]&0x40)); // wait until current command is complete
- context.flush = 0;
+ dsp5680xx_context.flush = 0;
- retval = eonce_move_value_at_r2_disp(target,0x00,HFM_CNFG); // write to HFM_CNFG (lock=0, select bank) -- flash_desc.bank&0x03,0x01 == 0x00,0x01 ???
+ retval = core_move_value_at_r2_disp(target,0x00,HFM_CNFG); // write to HFM_CNFG (lock=0, select bank) -- flash_desc.bank&0x03,0x01 == 0x00,0x01 ???
err_check_propagate(retval);
- retval = eonce_move_value_at_r2_disp(target,0x04,HFM_USTAT); // write to HMF_USTAT, clear PVIOL, ACCERR & BLANK bits
+ retval = core_move_value_at_r2_disp(target,0x04,HFM_USTAT); // write to HMF_USTAT, clear PVIOL, ACCERR & BLANK bits
err_check_propagate(retval);
- retval = eonce_move_value_at_r2_disp(target,0x10,HFM_USTAT); // clear only one bit at a time
+ retval = core_move_value_at_r2_disp(target,0x10,HFM_USTAT); // clear only one bit at a time
err_check_propagate(retval);
- retval = eonce_move_value_at_r2_disp(target,0x20,HFM_USTAT);
+ retval = core_move_value_at_r2_disp(target,0x20,HFM_USTAT);
err_check_propagate(retval);
- retval = eonce_move_value_at_r2_disp(target,0x00,HFM_PROT); // write to HMF_PROT, clear protection
+ retval = core_move_value_at_r2_disp(target,0x00,HFM_PROT); // write to HMF_PROT, clear protection
err_check_propagate(retval);
- retval = eonce_move_value_at_r2_disp(target,0x00,HFM_PROTB); // write to HMF_PROTB, clear protection
+ retval = core_move_value_at_r2_disp(target,0x00,HFM_PROTB); // write to HMF_PROTB, clear protection
err_check_propagate(retval);
- retval = eonce_move_value_to_y0(target,data);
+ retval = core_move_value_to_y0(target,data);
err_check_propagate(retval);
- retval = eonce_move_long_to_r3(target,address); // write to the flash block
+ retval = core_move_long_to_r3(target,address); // write to the flash block
err_check_propagate(retval);
if (pmem){
- retval = eonce_move_y0_at_pr3_inc(target);
+ retval = core_move_y0_at_pr3_inc(target);
err_check_propagate(retval);
}else{
- retval = eonce_move_y0_at_r3(target);
+ retval = core_move_y0_at_r3(target);
err_check_propagate(retval);
}
- retval = eonce_move_value_at_r2_disp(target,command,HFM_CMD); // write command to the HFM_CMD reg
+ retval = core_move_value_at_r2_disp(target,command,HFM_CMD); // write command to the HFM_CMD reg
err_check_propagate(retval);
- retval = eonce_move_value_at_r2_disp(target,0x80,HFM_USTAT); // start the command
+ retval = core_move_value_at_r2_disp(target,0x80,HFM_USTAT); // start the command
err_check_propagate(retval);
- context.flush = 1;
+ dsp5680xx_context.flush = 1;
retval = dsp5680xx_execute_queue();
err_check_propagate(retval);
watchdog = 100;
do{
- retval = eonce_move_at_r2_disp_to_y0(target,HFM_USTAT); // read HMF_USTAT
+ retval = core_move_at_r2_disp_to_y0(target,HFM_USTAT); // read HMF_USTAT
err_check_propagate(retval);
- retval = eonce_move_y0_at_r0(target);
+ retval = core_move_y0_at_r0(target);
err_check_propagate(retval);
- retval = eonce_rx_upper_data(target,&i);
+ retval = core_rx_upper_data(target,i);
err_check_propagate(retval);
if((watchdog--)==1){
retval = ERROR_TARGET_FAILURE;
err_check(retval,"FM execution did not finish.");
}
- }while (!(i&0x40)); // wait until the command is complete
- *hfm_ustat = i;
- if (i&HFM_USTAT_MASK_PVIOL_ACCER){
+ }while (!(i[0]&0x40)); // wait until the command is complete
+ *hfm_ustat = ((i[0]<<8)|(i[1]));
+ if (i[0]&HFM_USTAT_MASK_PVIOL_ACCER){
retval = ERROR_TARGET_FAILURE;
err_check(retval,"pviol and/or accer bits set. HFM command execution error");
}
*
* @return
*/
-static int eonce_set_hfmdiv(struct target * target){
- uint16_t i;
+static int set_fm_ck_div(struct target * target){
+ uint8_t i[2];
int retval;
- retval = eonce_move_long_to_r2(target,HFM_BASE_ADDR);
+ retval = core_move_long_to_r2(target,HFM_BASE_ADDR);
err_check_propagate(retval);
- retval = eonce_load_TX_RX_high_to_r0(target);
+ retval = core_load_TX_RX_high_addr_to_r0(target);
err_check_propagate(retval);
- retval = eonce_move_at_r2_to_y0(target);// read HFM_CLKD
+ retval = core_move_at_r2_to_y0(target);// read HFM_CLKD
err_check_propagate(retval);
- retval = eonce_move_y0_at_r0(target);
+ retval = core_move_y0_at_r0(target);
err_check_propagate(retval);
- retval = eonce_rx_upper_data(target,&i);
+ retval = core_rx_upper_data(target,i);
err_check_propagate(retval);
unsigned int hfm_at_wrong_value = 0;
- if ((i&0x7f)!=HFM_CLK_DEFAULT) {
- LOG_DEBUG("HFM CLK divisor contained incorrect value (0x%02X).",i&0x7f);
+ if ((i[0]&0x7f)!=HFM_CLK_DEFAULT) {
+ LOG_DEBUG("HFM CLK divisor contained incorrect value (0x%02X).",i[0]&0x7f);
hfm_at_wrong_value = 1;
}else{
- LOG_DEBUG("HFM CLK divisor was already set to correct value (0x%02X).",i&0x7f);
+ LOG_DEBUG("HFM CLK divisor was already set to correct value (0x%02X).",i[0]&0x7f);
return ERROR_OK;
}
- retval = eonce_move_value_at_r2(target,HFM_CLK_DEFAULT); // write HFM_CLKD
+ retval = core_move_value_at_r2(target,HFM_CLK_DEFAULT); // write HFM_CLKD
err_check_propagate(retval);
- retval = eonce_move_at_r2_to_y0(target); // verify HFM_CLKD
+ retval = core_move_at_r2_to_y0(target); // verify HFM_CLKD
err_check_propagate(retval);
- retval = eonce_move_y0_at_r0(target);
+ retval = core_move_y0_at_r0(target);
err_check_propagate(retval);
- retval = eonce_rx_upper_data(target,&i);
+ retval = core_rx_upper_data(target,i);
err_check_propagate(retval);
- if (i!=(0x80|(HFM_CLK_DEFAULT&0x7f))) {
+ if (i[0]!=(0x80|(HFM_CLK_DEFAULT&0x7f))) {
retval = ERROR_TARGET_FAILURE;
err_check(retval,"Unable to set HFM CLK divisor.");
}
if(hfm_at_wrong_value)
- LOG_DEBUG("HFM CLK divisor set to 0x%02x.",i&0x7f);
+ LOG_DEBUG("HFM CLK divisor set to 0x%02x.",i[0]&0x7f);
return ERROR_OK;
}
if (dsp5680xx_target_status(target,NULL,NULL) != TARGET_HALTED){
retval = eonce_enter_debug_mode(target,NULL);
err_check_propagate(retval);
+ // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ // Set hfmdiv
+ // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ retval = set_fm_ck_div(target);
+ err_check_propagate(retval);
}
retval = dsp5680xx_f_execute_command(target,HFM_CALCULATE_DATA_SIGNATURE,address,words,&hfm_ustat,1);
err_check_propagate(retval);
- retval = dsp5680xx_read_16_single(target, HFM_BASE_ADDR|HFM_DATA, signature, 0);
+ retval = dsp5680xx_read_16_single(target, HFM_BASE_ADDR|HFM_DATA, (uint8_t *)signature, 0);
return retval;
}
retval = dsp5680xx_halt(target);
err_check_propagate(retval);
}
+ retval = set_fm_ck_div(target);
+ err_check_propagate(retval);
// Check if chip is already erased.
retval = dsp5680xx_f_execute_command(target,HFM_ERASE_VERIFY,HFM_FLASH_BASE_ADDR+sector*HFM_SECTOR_SIZE/2,0,&hfm_ustat,1); // blank check
err_check_propagate(retval);
// -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
// Set hfmdiv
// -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- retval = eonce_set_hfmdiv(target);
+ retval = set_fm_ck_div(target);
err_check_propagate(retval);
uint16_t hfm_ustat;
const uint16_t pgm_write_pflash[] = {0x8A46,0x0013,0x407D,0xE700,0xE700,0x8A44,0xFFFE,0x017B,0xE700,0xF514,0x8563,0x8646,0x0020,0x0014,0x8646,0x0080,0x0013,0x8A46,0x0013,0x2004,0x8246,0x0013,0x0020,0xA968,0x8A46,0x0013,0x1065,0x8246,0x0013,0x0010,0xA961};
const uint32_t pgm_write_pflash_length = 31;
-int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, uint32_t count){
+int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, uint32_t count, int is_flash_lock){
int retval = ERROR_OK;
- uint16_t* buff16 = (uint16_t *) buffer;
if (dsp5680xx_target_status(target,NULL,NULL) != TARGET_HALTED){
retval = eonce_enter_debug_mode(target,NULL);
err_check_propagate(retval);
// Download the pgm that flashes.
// -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
uint32_t my_favourite_ram_address = 0x8700; // This seems to be a safe address. This one is the one used by codewarrior in 56801x_flash.cfg
- retval = dsp5680xx_write(target, my_favourite_ram_address, 1, pgm_write_pflash_length*2,(uint8_t *) pgm_write_pflash);
- err_check_propagate(retval);
- retval = dsp5680xx_execute_queue();
- err_check_propagate(retval);
+ if(!is_flash_lock){
+ retval = dsp5680xx_write(target, my_favourite_ram_address, 1, pgm_write_pflash_length*2,(uint8_t *) pgm_write_pflash);
+ err_check_propagate(retval);
+ retval = dsp5680xx_execute_queue();
+ err_check_propagate(retval);
+ }
// -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
// Set hfmdiv
// -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- retval = eonce_set_hfmdiv(target);
+ retval = set_fm_ck_div(target);
err_check_propagate(retval);
// -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
// Setup registers needed by pgm_write_pflash
// -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- context.flush = 0;
+ dsp5680xx_context.flush = 0;
- retval = eonce_move_long_to_r3(target,address); // Destination address to r3
+ retval = core_move_long_to_r3(target,address); // Destination address to r3
err_check_propagate(retval);
- eonce_load_TX_RX_high_to_r0(target); // TX/RX reg address to r0
+ core_load_TX_RX_high_addr_to_r0(target); // TX/RX reg address to r0
err_check_propagate(retval);
- retval = eonce_move_long_to_r2(target,HFM_BASE_ADDR);// FM base address to r2
+ retval = core_move_long_to_r2(target,HFM_BASE_ADDR);// FM base address to r2
err_check_propagate(retval);
// -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
// Run flashing program.
// -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- retval = eonce_move_value_at_r2_disp(target,0x00,HFM_CNFG); // write to HFM_CNFG (lock=0, select bank)
+ retval = core_move_value_at_r2_disp(target,0x00,HFM_CNFG); // write to HFM_CNFG (lock=0, select bank)
err_check_propagate(retval);
- retval = eonce_move_value_at_r2_disp(target,0x04,HFM_USTAT);// write to HMF_USTAT, clear PVIOL, ACCERR & BLANK bits
+ retval = core_move_value_at_r2_disp(target,0x04,HFM_USTAT);// write to HMF_USTAT, clear PVIOL, ACCERR & BLANK bits
err_check_propagate(retval);
- retval = eonce_move_value_at_r2_disp(target,0x10,HFM_USTAT);// clear only one bit at a time
+ retval = core_move_value_at_r2_disp(target,0x10,HFM_USTAT);// clear only one bit at a time
err_check_propagate(retval);
- retval = eonce_move_value_at_r2_disp(target,0x20,HFM_USTAT);
+ retval = core_move_value_at_r2_disp(target,0x20,HFM_USTAT);
err_check_propagate(retval);
- retval = eonce_move_value_at_r2_disp(target,0x00,HFM_PROT);// write to HMF_PROT, clear protection
+ retval = core_move_value_at_r2_disp(target,0x00,HFM_PROT);// write to HMF_PROT, clear protection
err_check_propagate(retval);
- retval = eonce_move_value_at_r2_disp(target,0x00,HFM_PROTB);// write to HMF_PROTB, clear protection
+ retval = core_move_value_at_r2_disp(target,0x00,HFM_PROTB);// write to HMF_PROTB, clear protection
err_check_propagate(retval);
if(count%2){
//TODO implement handling of odd number of words.
err_check(retval,"Cannot handle odd number of words.");
}
- context.flush = 1;
+ dsp5680xx_context.flush = 1;
retval = dsp5680xx_execute_queue();
err_check_propagate(retval);
uint32_t drscan_data;
- retval = eonce_tx_upper_data(target,buff16[0],&drscan_data);
+ uint16_t tmp = (buffer[0]|(buffer[1]<<8));
+ retval = core_tx_upper_data(target,tmp,&drscan_data);
err_check_propagate(retval);
retval = dsp5680xx_resume(target,0,my_favourite_ram_address,0,0);
err_check_propagate(retval);
int counter = FLUSH_COUNT_FLASH;
- context.flush = 0;
+ dsp5680xx_context.flush = 0;
uint32_t i;
for(i=1; (i<count/2)&&(i<HFM_SIZE_WORDS); i++){
if(--counter==0){
- context.flush = 1;
+ dsp5680xx_context.flush = 1;
counter = FLUSH_COUNT_FLASH;
}
- retval = eonce_tx_upper_data(target,buff16[i],&drscan_data);
+ tmp = (buffer[2*i]|(buffer[2*i+1]<<8));
+ retval = core_tx_upper_data(target,tmp,&drscan_data);
if(retval!=ERROR_OK){
- context.flush = 1;
+ dsp5680xx_context.flush = 1;
err_check_propagate(retval);
}
- context.flush = 0;
+ dsp5680xx_context.flush = 0;
}
- context.flush = 1;
- // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- // Verify flash
- // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- uint16_t signature;
- uint16_t pc_crc;
- retval = dsp5680xx_f_signature(target,address,i,&signature);
- err_check_propagate(retval);
- pc_crc = perl_crc(buff16,i);
- if(pc_crc != signature){
- retval = ERROR_FAIL;
- err_check(retval,"Flashed data failed CRC check, flash again!");
+ dsp5680xx_context.flush = 1;
+ if(!is_flash_lock){
+ // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ // Verify flash (skip when exec lock sequence)
+ // -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ uint16_t signature;
+ uint16_t pc_crc;
+ retval = dsp5680xx_f_signature(target,address,i,&signature);
+ err_check_propagate(retval);
+ pc_crc = perl_crc(buffer,i);
+ if(pc_crc != signature){
+ retval = ERROR_FAIL;
+ err_check(retval,"Flashed data failed CRC check, flash again!");
+ }
}
return retval;
}
-int dsp5680xx_f_unlock(struct target * target){
+// Reset state machine
+int reset_jtag(void){
int retval;
- if(target->tap->enabled){
- //TODO find a way to switch to the master tap here.
- LOG_ERROR("Master tap must be enabled to unlock flash.");
- return ERROR_TARGET_FAILURE;
+ tap_state_t states[2];
+ const char *cp = "RESET";
+ states[0] = tap_state_by_name(cp);
+ retval = jtag_add_statemove(states[0]);
+ err_check_propagate(retval);
+ retval = jtag_execute_queue();
+ err_check_propagate(retval);
+ jtag_add_pathmove(0, states + 1);
+ retval = jtag_execute_queue();
+ return retval;
+}
+
+int dsp5680xx_f_unlock(struct target * target){
+ int retval = ERROR_OK;
+ uint16_t eonce_status;
+ uint32_t instr;
+ uint32_t ir_out;
+ uint16_t instr_16;
+ uint16_t read_16;
+ struct jtag_tap * tap_chp;
+ struct jtag_tap * tap_cpu;
+ tap_chp = jtag_tap_by_string("dsp568013.chp");
+ if(tap_chp == NULL){
+ retval = ERROR_FAIL;
+ err_check(retval,"Failed to get master tap.");
}
- uint32_t data_to_shift_in = MASTER_TAP_CMD_FLASH_ERASE;
- uint32_t data_shifted_out;
- retval = dsp5680xx_irscan(target,&data_to_shift_in,&data_shifted_out,8);
+ tap_cpu = jtag_tap_by_string("dsp568013.cpu");
+ if(tap_cpu == NULL){
+ retval = ERROR_FAIL;
+ err_check(retval,"Failed to get master tap.");
+ }
+
+ retval = eonce_enter_debug_mode(target,&eonce_status);
+ if(retval == ERROR_OK){
+ LOG_WARNING("Memory was not locked.");
+ return retval;
+ }
+
+ jtag_add_reset(0,1);
+ usleep(TIME_DIV_FREESCALE*200*1000);
+
+ retval = reset_jtag();
+ err_check(retval,"Failed to reset JTAG state machine");
+ usleep(150);
+
+ // Enable core tap
+ tap_chp->enabled = true;
+ retval = switch_tap(target,tap_chp,tap_cpu);
+ err_check_propagate(retval);
+
+ instr = JTAG_INSTR_DEBUG_REQUEST;
+ retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
+ err_check_propagate(retval);
+ usleep(TIME_DIV_FREESCALE*100*1000);
+ jtag_add_reset(0,0);
+ usleep(TIME_DIV_FREESCALE*300*1000);
+
+ // Enable master tap
+ retval = switch_tap(target,tap_chp,tap_cpu);
+ err_check_propagate(retval);
+
+ // Execute mass erase to unlock
+ instr = MASTER_TAP_CMD_FLASH_ERASE;
+ retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_MASTER_TAP_IRLEN);
+ err_check_propagate(retval);
+
+ instr = HFM_CLK_DEFAULT;
+ retval = dsp5680xx_drscan(target,(uint8_t *) & instr,(uint8_t *) & ir_out,16);
+ err_check_propagate(retval);
+
+ usleep(TIME_DIV_FREESCALE*150*1000);
+ jtag_add_reset(0,1);
+ usleep(TIME_DIV_FREESCALE*200*1000);
+
+ retval = reset_jtag();
+ err_check(retval,"Failed to reset JTAG state machine");
+ usleep(150);
+
+ instr = 0x0606ffff;
+ retval = dsp5680xx_drscan(target,(uint8_t *) & instr,(uint8_t *) & ir_out,32);
+ err_check_propagate(retval);
+
+ // enable core tap
+ instr = 0x5;
+ retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_MASTER_TAP_IRLEN);
+ err_check_propagate(retval);
+ instr = 0x2;
+ retval = dsp5680xx_drscan(target,(uint8_t *) & instr,(uint8_t *) & ir_out,4);
+ err_check_propagate(retval);
+
+ tap_cpu->enabled = true;
+ tap_chp->enabled = false;
+
+ instr = JTAG_INSTR_ENABLE_ONCE;
+ //Two rounds of jtag 0x6 (enable eonce) to enable EOnCE.
+ retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
err_check_propagate(retval);
- data_to_shift_in = HFM_CLK_DEFAULT;
- retval = dsp5680xx_drscan(target,((uint8_t *) & data_to_shift_in),((uint8_t *)&data_shifted_out),8);
+ instr = JTAG_INSTR_DEBUG_REQUEST;
+ retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
err_check_propagate(retval);
+ instr_16 = 0x1;
+ retval = dsp5680xx_drscan(target,(uint8_t *) & instr_16,(uint8_t *) & read_16,8);
+ instr_16 = 0x20;
+ retval = dsp5680xx_drscan(target,(uint8_t *) & instr_16,(uint8_t *) & read_16,8);
+ usleep(TIME_DIV_FREESCALE*100*1000);
+ jtag_add_reset(0,0);
+ usleep(TIME_DIV_FREESCALE*300*1000);
return retval;
}
int dsp5680xx_f_lock(struct target * target){
int retval;
uint16_t lock_word[] = {HFM_LOCK_FLASH,HFM_LOCK_FLASH};
- retval = dsp5680xx_f_wr(target,(uint8_t *)(lock_word),HFM_LOCK_ADDR_L,4);
+ retval = dsp5680xx_f_wr(target,(uint8_t *)(lock_word),HFM_LOCK_ADDR_L,4,1);
err_check_propagate(retval);
return retval;
+ jtag_add_reset(0,1);
+ usleep(TIME_DIV_FREESCALE*200*1000);
+
+ retval = reset_jtag();
+ err_check(retval,"Failed to reset JTAG state machine");
+ usleep(TIME_DIV_FREESCALE*100*1000);
+ jtag_add_reset(0,0);
+ usleep(TIME_DIV_FREESCALE*300*1000);
+
+ return retval;
}
static int dsp5680xx_step(struct target * target,int current, uint32_t address, int handle_breakpoints){
Code Review / openocd.git / blobdiff