-#define ASM_REG_W_R0 0x60F400
-#define ASM_REG_W_R1 0x61F400
-#define ASM_REG_W_R2 0x62F400
-#define ASM_REG_W_R3 0x63F400
-#define ASM_REG_W_R4 0x64F400
-#define ASM_REG_W_R5 0x65F400
-#define ASM_REG_W_R6 0x66F400
-#define ASM_REG_W_R7 0x67F400
-
-#define ASM_REG_W_N0 0x70F400
-#define ASM_REG_W_N1 0x71F400
-#define ASM_REG_W_N2 0x72F400
-#define ASM_REG_W_N3 0x73F400
-#define ASM_REG_W_N4 0x74F400
-#define ASM_REG_W_N5 0x75F400
-#define ASM_REG_W_N6 0x76F400
-#define ASM_REG_W_N7 0x77F400
-
-#define ASM_REG_W_M0 0x05F420
-#define ASM_REG_W_M1 0x05F421
-#define ASM_REG_W_M2 0x05F422
-#define ASM_REG_W_M3 0x05F423
-#define ASM_REG_W_M4 0x05F424
-#define ASM_REG_W_M5 0x05F425
-#define ASM_REG_W_M6 0x05F426
-#define ASM_REG_W_M7 0x05F427
-
-#define ASM_REG_W_X0 0x44F400
-#define ASM_REG_W_X1 0x45F400
-
-#define ASM_REG_W_Y0 0x46F400
-#define ASM_REG_W_Y1 0x47F400
-
-#define ASM_REG_W_A0 0x50F400
-#define ASM_REG_W_A1 0x54F400
-#define ASM_REG_W_A2 0x52F400
-
-#define ASM_REG_W_B0 0x51F400
-#define ASM_REG_W_B1 0x55F400
-#define ASM_REG_W_B2 0x53F400
-
-#define ASM_REG_W_VBA 0x05F430
-#define ASM_REG_W_OMR 0x05F43A
-#define ASM_REG_W_EP 0x05F42A
-#define ASM_REG_W_SC 0x05F431
-#define ASM_REG_W_SZ 0x05F438
-#define ASM_REG_W_SR 0x05F439
-#define ASM_REG_W_SP 0x05F43B
-#define ASM_REG_W_SSH 0x05F43C
-#define ASM_REG_W_SSL 0x05F43D
-#define ASM_REG_W_LA 0x05F43E
-#define ASM_REG_W_LC 0x05F43F
-#define ASM_REG_W_PC 0x000000
-#define ASM_REG_W_IPRC 0xFFFFFF
-#define ASM_REG_W_IPRP 0xFFFFFE
-
-#define ASM_REG_W_BCR 0xFFFFFB
-#define ASM_REG_W_DCR 0xFFFFFA
-#define ASM_REG_W_AAR0 0xFFFFF9
-#define ASM_REG_W_AAR1 0xFFFFF8
-#define ASM_REG_W_AAR2 0xFFFFF7
-#define ASM_REG_W_AAR3 0xFFFFF6
+#define ASM_REG_W_R0 0x60F400
+#define ASM_REG_W_R1 0x61F400
+#define ASM_REG_W_R2 0x62F400
+#define ASM_REG_W_R3 0x63F400
+#define ASM_REG_W_R4 0x64F400
+#define ASM_REG_W_R5 0x65F400
+#define ASM_REG_W_R6 0x66F400
+#define ASM_REG_W_R7 0x67F400
+
+#define ASM_REG_W_N0 0x70F400
+#define ASM_REG_W_N1 0x71F400
+#define ASM_REG_W_N2 0x72F400
+#define ASM_REG_W_N3 0x73F400
+#define ASM_REG_W_N4 0x74F400
+#define ASM_REG_W_N5 0x75F400
+#define ASM_REG_W_N6 0x76F400
+#define ASM_REG_W_N7 0x77F400
+
+#define ASM_REG_W_M0 0x05F420
+#define ASM_REG_W_M1 0x05F421
+#define ASM_REG_W_M2 0x05F422
+#define ASM_REG_W_M3 0x05F423
+#define ASM_REG_W_M4 0x05F424
+#define ASM_REG_W_M5 0x05F425
+#define ASM_REG_W_M6 0x05F426
+#define ASM_REG_W_M7 0x05F427
+
+#define ASM_REG_W_X0 0x44F400
+#define ASM_REG_W_X1 0x45F400
+
+#define ASM_REG_W_Y0 0x46F400
+#define ASM_REG_W_Y1 0x47F400
+
+#define ASM_REG_W_A0 0x50F400
+#define ASM_REG_W_A1 0x54F400
+#define ASM_REG_W_A2 0x52F400
+
+#define ASM_REG_W_B0 0x51F400
+#define ASM_REG_W_B1 0x55F400
+#define ASM_REG_W_B2 0x53F400
+
+#define ASM_REG_W_VBA 0x05F430
+#define ASM_REG_W_OMR 0x05F43A
+#define ASM_REG_W_EP 0x05F42A
+#define ASM_REG_W_SC 0x05F431
+#define ASM_REG_W_SZ 0x05F438
+#define ASM_REG_W_SR 0x05F439
+#define ASM_REG_W_SP 0x05F43B
+#define ASM_REG_W_SSH 0x05F43C
+#define ASM_REG_W_SSL 0x05F43D
+#define ASM_REG_W_LA 0x05F43E
+#define ASM_REG_W_LC 0x05F43F
+#define ASM_REG_W_PC 0x000000
+#define ASM_REG_W_IPRC 0xFFFFFF
+#define ASM_REG_W_IPRP 0xFFFFFE
+
+#define ASM_REG_W_BCR 0xFFFFFB
+#define ASM_REG_W_DCR 0xFFFFFA
+#define ASM_REG_W_AAR0 0xFFFFF9
+#define ASM_REG_W_AAR1 0xFFFFF8
+#define ASM_REG_W_AAR2 0xFFFFF7
+#define ASM_REG_W_AAR3 0xFFFFF6
+
+/*
+ * OBCR Register bit definitions
+ */
+#define OBCR_b0_and_b1 ((0x0) << 10)
+#define OBCR_b0_or_b1 ((0x1) << 10)
+#define OBCR_b1_after_b0 ((0x2) << 10)
+#define OBCR_b0_after_b1 ((0x3) << 10)
+
+#define OBCR_BP_DISABLED (0x0)
+#define OBCR_BP_MEM_P (0x1)
+#define OBCR_BP_MEM_X (0x2)
+#define OBCR_BP_MEM_Y (0x3)
+#define OBCR_BP_ON_READ ((0x2) << 0)
+#define OBCR_BP_ON_WRITE ((0x1) << 0)
+#define OBCR_BP_CC_NOT_EQUAL ((0x0) << 2)
+#define OBCR_BP_CC_EQUAL ((0x1) << 2)
+#define OBCR_BP_CC_LESS_THAN ((0x2) << 2)
+#define OBCR_BP_CC_GREATER_THAN ((0x3) << 2)
+
+#define OBCR_BP_0(x) ((x)<<2)
+#define OBCR_BP_1(x) ((x)<<6)
+
+
+enum once_reg_idx {
+ ONCE_REG_IDX_OSCR = 0,
+ ONCE_REG_IDX_OMBC = 1,
+ ONCE_REG_IDX_OBCR = 2,
+ ONCE_REG_IDX_OMLR0 = 3,
+ ONCE_REG_IDX_OMLR1 = 4,
+ ONCE_REG_IDX_OGDBR = 5,
+ ONCE_REG_IDX_OPDBR = 6,
+ ONCE_REG_IDX_OPILR = 7,
+ ONCE_REG_IDX_PDB = 8,
+ ONCE_REG_IDX_OTC = 9,
+ ONCE_REG_IDX_OPABFR = 10,
+ ONCE_REG_IDX_OPABDR = 11,
+ ONCE_REG_IDX_OPABEX = 12,
+ ONCE_REG_IDX_OPABF0 = 13,
+ ONCE_REG_IDX_OPABF1 = 14,
+ ONCE_REG_IDX_OPABF2 = 15,
+ ONCE_REG_IDX_OPABF3 = 16,
+ ONCE_REG_IDX_OPABF4 = 17,
+ ONCE_REG_IDX_OPABF5 = 18,
+ ONCE_REG_IDX_OPABF6 = 19,
+ ONCE_REG_IDX_OPABF7 = 20,
+ ONCE_REG_IDX_OPABF8 = 21,
+ ONCE_REG_IDX_OPABF9 = 22,
+ ONCE_REG_IDX_OPABF10 = 23,
+ ONCE_REG_IDX_OPABF11 = 24,
+};