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[openocd.git] / src / target / cortex_swjdp.c
diff --git a/src/target/cortex_swjdp.c b/src/target/cortex_swjdp.c
index 2a2267ffb5d4597999c5246697cbc9a7804ae6c9..6f26790741e2f1d4efb62c77c9315a3375599bdf 100644 (file)
--- a/src/target/cortex_swjdp.c
+++ b/src/target/cortex_swjdp.c
@@ -22,7 +22,7 @@
  * CoreSight (Light?) SerialWireJtagDebugPort                              *
  *                                                                         *
  * CoreSight™ DAP-Lite TRM, ARM DDI 0316A                                  *
- * Cortex-M3™ TRM, ARM DDI 0337C                                            *
+ * Cortex-M3™ TRM, ARM DDI 0337C                                           *
  *                                                                         *
 ***************************************************************************/
 #ifdef HAVE_CONFIG_H
@@ -87,7 +87,7 @@ int swjdp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalu
        fields[1].in_check_value = NULL;
        fields[1].in_check_mask = NULL;
 
-       jtag_add_dr_scan(2, fields, -1, NULL);
+       jtag_add_dr_scan(2, fields, -1);
 
        return ERROR_OK;
 }
@@ -132,7 +132,7 @@ int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 out
        fields[1].in_check_value = NULL;
        fields[1].in_check_mask = NULL;
 
-       jtag_add_dr_scan(2, fields, -1, NULL);
+       jtag_add_dr_scan(2, fields, -1);
 
        return ERROR_OK;
 }
@@ -164,7 +164,7 @@ int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u
                swjdp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, 0xC, DPAP_READ, 0, invalue, &swjdp->ack);
        }
        
-       /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
+       /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */
        if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
        {
                return swjdp_transaction_endcheck(swjdp);
@@ -178,6 +178,7 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
        int waitcount = 0;
        u32 ctrlstat;
 
+       scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
        scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
        jtag_execute_queue();
        
@@ -191,6 +192,7 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
                        if (waitcount > 100)
                        {
                                WARNING("Timeout waiting for ACK = OK/FAULT in SWJDP transaction");
+
                                return ERROR_JTAG_DEVICE_ERROR;
                        }
                }
@@ -199,6 +201,7 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
                        WARNING("Invalid ACK in SWJDP transaction");
                        return ERROR_JTAG_DEVICE_ERROR;
                }
+
                scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
                jtag_execute_queue();
                swjdp->ack = swjdp->ack & 0x7;
@@ -324,13 +327,13 @@ int ahbap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar)
        csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
        if (csw != swjdp->ap_csw_value)
        {
-               //DEBUG("swjdp : Set CSW %x",csw);
+               /* DEBUG("swjdp : Set CSW %x",csw); */
                ahbap_write_reg_u32(swjdp, AHBAP_CSW, csw ); 
                swjdp->ap_csw_value = csw;
        }
        if (tar != swjdp->ap_tar_value)
        {
-               //DEBUG("swjdp : Set TAR %x",tar);
+               /* DEBUG("swjdp : Set TAR %x",tar); */
                ahbap_write_reg_u32(swjdp, AHBAP_TAR, tar );
                swjdp->ap_tar_value = tar;
        }
@@ -418,7 +421,7 @@ int ahbap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
        count = count - 4 * wcount;
        while (wcount > 0)
        {
-               /* Adjust to read within 4K block boundaries */
+               /* Adjust to write blocks within 4K aligned boundaries */
                blocksize = (0x1000 - (0xFFF & address)) >> 2;
                if (wcount < blocksize)
                        blocksize = wcount;
@@ -439,7 +442,7 @@ int ahbap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
                }
                if (errorcount > 1)
                {
-                       WARNING("Block read error address 0x%x, count 0x%x", address, count);
+                       WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount);
                        return ERROR_JTAG_DEVICE_ERROR;
                }
        }
@@ -573,7 +576,7 @@ int ahbap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address
 int ahbap_block_read_u32(swjdp_common_t *swjdp, u32 *buffer, int count, u32 address)
 {
        int readcount, errorcount = 0;
-       u32 blockmax, blocksize;
+       u32 blocksize;
        
        swjdp->trans_mode = TRANS_MODE_COMPOSITE;
        
@@ -610,6 +613,11 @@ int ahbap_block_read_u32(swjdp_common_t *swjdp, u32 *buffer, int count, u32 addr
 
 int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
 {
+       int retval;
+       u32 dcrdr;
+       
+       ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr);
+       
        swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 
        /* ahbap_write_system_u32(swjdp, DCB_DCRSR, regnum); */
@@ -620,11 +628,18 @@ int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
        ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
        ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
        
-       return swjdp_transaction_endcheck(swjdp);
+       retval = swjdp_transaction_endcheck(swjdp);
+       ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
+       return retval;
 }
 
 int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
 {
+       int retval;
+       u32 dcrdr;
+       
+       ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr);
+       
        swjdp->trans_mode = TRANS_MODE_COMPOSITE;
        
        /* ahbap_write_system_u32(swjdp, DCB_DCRDR, core_regs[i]); */
@@ -634,8 +649,10 @@ int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
        /* ahbap_write_system_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR       ); */
        ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
        ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR );
-
-       return swjdp_transaction_endcheck(swjdp);
+       
+       retval = swjdp_transaction_endcheck(swjdp);
+       ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
+       return retval;
 }
 
 int ahbap_debugport_init(swjdp_common_t *swjdp)
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