/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
+ * *
* Copyright (C) 2006 by Magnus Lundin *
* lundin@mlu.mine.nu *
* *
#define DCB_DCRDR 0xE000EDF8
#define DCB_DEMCR 0xE000EDFC
-
#define DCRSR_WnR (1<<16)
#define DWT_CTRL 0xE0001000
/* NVIC_SHCSR bits */
#define SHCSR_BUSFAULTENA (1<<17)
/* NVIC_DFSR bits */
-#define DFSR_HALTED 1
-#define DFSR_BKPT 2
-#define DFSR_DWTTRAP 4
-#define DFSR_VCATCH 8
-
+#define DFSR_HALTED 1
+#define DFSR_BKPT 2
+#define DFSR_DWTTRAP 4
+#define DFSR_VCATCH 8
#define FPCR_CODE 0
#define FPCR_LITERAL 1
int fp_num_code;
int fp_code_available;
int auto_bp_type;
- cortex_m3_fp_comparator_t * fp_comparator_list;
+ cortex_m3_fp_comparator_t *fp_comparator_list;
/* DWT */
int dwt_num_comp;
int dwt_comp_available;
- cortex_m3_dwt_comparator_t * dwt_comparator_list;
+ cortex_m3_dwt_comparator_t *dwt_comparator_list;
/* Interrupts */
int intlinesnum;
- u32 * intsetenable;
+ u32 *intsetenable;
/*
u32 arm_bkpt;
void *arch_info;
} cortex_m3_common_t;
-
extern void cortex_m3_build_reg_cache(target_t *target);
-enum target_state cortex_m3_poll(target_t *target);
+int cortex_m3_poll(target_t *target);
int cortex_m3_halt(target_t *target);
int cortex_m3_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
int cortex_m3_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
int cortex_m3_assert_reset(target_t *target);
int cortex_m3_deassert_reset(target_t *target);
int cortex_m3_soft_reset_halt(struct target_s *target);
+int cortex_m3_prepare_reset_halt(struct target_s *target);
int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);