Zach Welch <zw@superlucidity.net> fix -Werror warnings

[openocd.git] / src / target / cortex_m3.c

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index d938210ad62d499736f31e4b22b4ed4902003631..f07bef0816f21c203021e6aec677b2ec91e71e8d 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -44,6 +44,7 @@
 
 /* cli handling */
 int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
+int handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 
 /* forward declarations */
 void cortex_m3_enable_breakpoints(struct target_s *target);
@@ -224,6 +225,7 @@ int cortex_m3_endreset_event(target_t *target)
 
        /* Enable FPB */
        target_write_u32(target, FP_CTRL, 3);
+       cortex_m3->fpb_enabled = 1;
 
        /* Restore FPB registers */
        for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
@@ -241,6 +243,10 @@ int cortex_m3_endreset_event(target_t *target)
        swjdp_transaction_endcheck(swjdp);
        
        armv7m_invalidate_core_regs(target);
+       
+       /* make sure we have latest dhcsr flags */
+       ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+       
        return ERROR_OK;
 }
 
@@ -722,8 +728,12 @@ int cortex_m3_assert_reset(target_t *target)
                /* Set/Clear C_MASKINTS in a separate operation */
                if (cortex_m3->dcb_dhcsr & C_MASKINTS)
                        ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT);
-       
+
+               /* clear any debug flags before resuming */
                cortex_m3_clear_halt(target);
+               
+               /* clear C_HALT in dhcsr reg */
+               cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
                                                        
                /* Enter debug state on reset, cf. end_reset_event() */ 
                ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
@@ -738,7 +748,7 @@ int cortex_m3_assert_reset(target_t *target)
         * when srst is asserted the luminary device seesm to also clear the debug registers
         * which does not match the armv7 debug TRM */
                
-       if (strcmp(cortex_m3->variant, "lm3s") == 0)
+       if (strcmp(target->variant, "lm3s") == 0)
        {
                /* get revision of lm3s target, only early silicon has this issue
                 * Fury Rev B, DustDevil Rev B, Tempest all ok */
@@ -868,6 +878,11 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
                target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
                LOG_DEBUG("fpc_num %i fpcr_value 0x%x", fp_num, comparator_list[fp_num].fpcr_value);
+               if (!cortex_m3->fpb_enabled)
+               {
+                       LOG_DEBUG("FPB wasn't enabled, do it now");
+                       target_write_u32(target, FP_CTRL, 3);
+               }
        }
        else if (breakpoint->type == BKPT_SOFT)
        {
@@ -1400,10 +1415,11 @@ int cortex_m3_examine(struct target_s *target)
                /* Setup FPB */
                target_read_u32(target, FP_CTRL, &fpcr);
                cortex_m3->auto_bp_type = 1;
-               cortex_m3->fp_num_code = (fpcr >> 4) & 0xF;
+               cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
                cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
                cortex_m3->fp_code_available = cortex_m3->fp_num_code;
                cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t));
+               cortex_m3->fpb_enabled = fpcr & 1;
                for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
                {
                        cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
@@ -1459,7 +1475,7 @@ int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer)
        swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
        u8 data;
        u8 ctrl;
-       int i;
+       u32 i;
        
        for (i = 0; i < (size * 4); i++)
        {
@@ -1509,13 +1525,13 @@ int cortex_m3_handle_target_request(void *priv)
        return ERROR_OK;
 }
 
-int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, int chain_pos, const char *variant)
+int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap)
 {
        armv7m_common_t *armv7m;
        armv7m = &cortex_m3->armv7m;
 
        /* prepare JTAG information for the new target */
-       cortex_m3->jtag_info.chain_pos = chain_pos;
+       cortex_m3->jtag_info.tap = tap;
        cortex_m3->jtag_info.scann_size = 4;
        
        cortex_m3->swjdp_info.dp_select_value = -1;
@@ -1537,15 +1553,6 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, in
        armv7m->pre_restore_context = NULL;
        armv7m->post_restore_context = NULL;
        
-       if (variant)
-       {
-               cortex_m3->variant = strdup(variant);
-       }
-       else
-       {
-               cortex_m3->variant = strdup("");
-       }
-       
        armv7m_init_arch_info(target, armv7m);  
        armv7m->arch_info = cortex_m3;
        armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
@@ -1560,7 +1567,7 @@ int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp)
 {
        cortex_m3_common_t *cortex_m3 = calloc(1,sizeof(cortex_m3_common_t));
        
-       cortex_m3_init_arch_info(target, cortex_m3, target->chain_position, target->variant);
+       cortex_m3_init_arch_info(target, cortex_m3, target->tap);
        
        return ERROR_OK;
 }
@@ -1568,8 +1575,46 @@ int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp)
 int cortex_m3_register_commands(struct command_context_s *cmd_ctx)
 {
        int retval;
+       command_t *cortex_m3_cmd;
        
        retval = armv7m_register_commands(cmd_ctx);
        
+       cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3", NULL, COMMAND_ANY, "cortex_m3 specific commands");         
+       register_command(cmd_ctx, cortex_m3_cmd, "maskisr", handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC, "mask cortex_m3 interrupts ['on'|'off']");
+       
        return retval;
 }
+
+int handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+       target_t *target = get_current_target(cmd_ctx);
+       armv7m_common_t *armv7m = target->arch_info;
+       cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
+               
+       if (target->state != TARGET_HALTED)
+       {
+               command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
+               return ERROR_OK;
+       }
+       
+       if (argc > 0)
+       {
+               if (!strcmp(args[0], "on"))
+               {
+                       cortex_m3_write_debug_halt_mask(target, C_HALT|C_MASKINTS, 0);
+               }
+               else if (!strcmp(args[0], "off"))
+               {
+                       cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
+               }
+               else
+               {
+                       command_print(cmd_ctx, "usage: cortex_m3 maskisr ['on'|'off']");
+               }
+       }
+       
+       command_print(cmd_ctx, "cortex_m3 interrupt mask %s",
+                       (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off");
+       
+       return ERROR_OK;
+}