* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
* *
* *
- * Cortex-M3(tm) TRM, ARM DDI 0337C *
+ * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
* *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "cortex_m3.h"
#include "target_request.h"
#include "target_type.h"
+#include "arm_disassembler.h"
+
+
+#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
/* cli handling */
/* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
- dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum );
+ dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
/* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
- dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value );
+ dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr);
retval = swjdp_transaction_endcheck(swjdp);
/* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
- dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value );
+ dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
- /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */
+ /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
- dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR );
+ dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr);
retval = swjdp_transaction_endcheck(swjdp);
/* Read Debug Fault Status Register */
mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
- /* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */
+ /* Clear Debug Fault Status */
mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
return ERROR_OK;
}
-int cortex_m3_exec_opcode(target_t *target,uint32_t opcode, int len /* MODE, r0_invalue, &r0_outvalue */ )
+int cortex_m3_exec_opcode(target_t *target,uint32_t opcode, int len /* MODE, r0_invalue, &r0_outvalue */)
{
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
if ((target->debug_reason != DBG_REASON_DBGRQ)
&& (target->debug_reason != DBG_REASON_SINGLESTEP))
{
- /* INCOMPLETE */
-
if (cortex_m3->nvic_dfsr & DFSR_BKPT)
{
target->debug_reason = DBG_REASON_BREAKPOINT;
}
else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
target->debug_reason = DBG_REASON_WATCHPOINT;
+ else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
+ target->debug_reason = DBG_REASON_BREAKPOINT;
+ else /* EXTERNAL, HALTED, DWTTRAP w/o BKPT */
+ target->debug_reason = DBG_REASON_UNDEFINED;
}
return ERROR_OK;
/* Examine target state and mode */
/* First load register acessible through core debug port*/
- for (i = 0; i < ARMV7M_PRIMASK; i++)
+ int num_regs = armv7m->core_cache->num_regs;
+
+ for (i = 0; i < num_regs; i++)
{
if (!armv7m->core_cache->reg_list[i].valid)
armv7m->read_core_reg(target, i);
cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
}
- /* Now we can load SP core registers */
- for (i = ARMV7M_PRIMASK; i < ARMV7NUMCOREREGS; i++)
- {
- if (!armv7m->core_cache->reg_list[i].valid)
- armv7m->read_core_reg(target, i);
- }
-
/* Are we in an exception handler */
if (xPSR & 0x1FF)
{
LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
armv7m_mode_strings[armv7m->core_mode],
*(uint32_t*)(armv7m->core_cache->reg_list[15].value),
- Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
+ target_state_name(target));
if (armv7m->post_debug_entry)
armv7m->post_debug_entry(target);
}
}
- /*
- if (cortex_m3->dcb_dhcsr & S_SLEEP)
- target->state = TARGET_SLEEP;
- */
+ /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
+ * How best to model low power modes?
+ */
-#if 0
- /* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */
- mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
- LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
-#endif
+ if (target->state == TARGET_UNKNOWN)
+ {
+ /* check if processor is retiring instructions */
+ if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
+ {
+ target->state = TARGET_RUNNING;
+ return ERROR_OK;
+ }
+ }
return ERROR_OK;
}
int cortex_m3_halt(target_t *target)
{
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
+ target_state_name(target));
if (target->state == TARGET_HALTED)
{
/* Single step past breakpoint at current address */
if ((breakpoint = breakpoint_find(target, resume_pc)))
{
- LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
+ LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
+ breakpoint->address,
+ breakpoint->unique_id );
cortex_m3_unset_breakpoint(target, breakpoint);
cortex_m3_single_step_core(target);
cortex_m3_set_breakpoint(target, breakpoint);
return ERROR_OK;
}
-/* int irqstepcount=0; */
+/* int irqstepcount = 0; */
int cortex_m3_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
{
/* get pointers to arch-specific information */
int assert_srst = 1;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
+ target_state_name(target));
enum reset_types jtag_reset_config = jtag_get_reset_config();
+
+ /*
+ * We can reset Cortex-M3 targets using just the NVIC without
+ * requiring SRST, getting a SoC reset (or a core-only reset)
+ * instead of a system reset.
+ */
if (!(jtag_reset_config & RESET_HAS_SRST))
- {
- LOG_ERROR("Can't assert SRST");
- return ERROR_FAIL;
- }
+ assert_srst = 0;
/* Enable debug requests */
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
- mem_ap_write_u32(swjdp, DCB_DCRDR, 0 );
+ mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
if (!target->reset_halt)
{
mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
}
- /* following hack is to handle luminary reset
- * when srst is asserted the luminary device seesm to also clear the debug registers
- * which does not match the armv7 debug TRM */
-
+ /*
+ * When nRST is asserted on most Stellaris devices, it clears some of
+ * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
+ * and OpenOCD depends on those TRMs. So we won't use SRST on those
+ * chips. (Only power-on reset should affect debug state, beyond a
+ * few specified bits; not the chip's nRST input, wired to SRST.)
+ *
+ * REVISIT current errata specs don't seem to cover this issue.
+ * Do we have more details than this email?
+ * https://lists.berlios.de/pipermail
+ * /openocd-development/2008-August/003065.html
+ */
if (strcmp(target->variant, "lm3s") == 0)
{
- /* get revision of lm3s target, only early silicon has this issue
- * Fury Rev B, DustDevil Rev B, Tempest all ok */
-
+ /* Check for silicon revisions with the issue. */
uint32_t did0;
if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
case 1:
case 3:
- /* only Fury/DustDevil rev A suffer reset problems */
+ /* Fury and DustDevil rev A have
+ * this nRST problem. It should
+ * be fixed in rev B silicon.
+ */
if (((did0 >> 8) & 0xff) == 0)
assert_srst = 0;
break;
+ case 4:
+ /* Tempest should be fine. */
+ break;
}
}
}
}
else
{
- /* this causes the luminary device to reset using the watchdog */
- mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
- LOG_DEBUG("Using Luminary Reset: SYSRESETREQ");
+ /* Use a standard Cortex-M3 software reset mechanism.
+ * SYSRESETREQ will reset SoC peripherals outside the
+ * core, like watchdog timers, if the SoC wires it up
+ * correctly. Else VECRESET can reset just the core.
+ */
+ mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
+ AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
+ LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
{
- /* I do not know why this is necessary, but it fixes strange effects
- * (step/resume cause a NMI after reset) on LM3S6918 -- Michael Schwingen */
+ /* I do not know why this is necessary, but it
+ * fixes strange effects (step/resume cause NMI
+ * after reset) on LM3S6918 -- Michael Schwingen
+ */
uint32_t tmp;
mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
}
int cortex_m3_deassert_reset(target_t *target)
{
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
+ target_state_name(target));
/* deassert reset lines */
jtag_add_reset(0, 0);
int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval;
- int fp_num=0;
+ int fp_num = 0;
uint32_t hilo;
/* get pointers to arch-specific information */
if (breakpoint->set)
{
- LOG_WARNING("breakpoint already set");
+ LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
return ERROR_OK;
}
breakpoint->set = 0x11; /* Any nice value but 0 */
}
+ LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
+ breakpoint->unique_id,
+ (int)(breakpoint->type),
+ breakpoint->address,
+ breakpoint->length,
+ breakpoint->set);
+
return ERROR_OK;
}
return ERROR_OK;
}
+ LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
+ breakpoint->unique_id,
+ (int)(breakpoint->type),
+ breakpoint->address,
+ breakpoint->length,
+ breakpoint->set);
+
if (breakpoint->type == BKPT_HARD)
{
int fp_num = breakpoint->set - 1;
int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
- int dwt_num=0;
+ int dwt_num = 0;
uint32_t mask, temp;
/* get pointers to arch-specific information */
if (watchpoint->set)
{
- LOG_WARNING("watchpoint already set");
+ LOG_WARNING("watchpoint (%d) already set", watchpoint->unique_id );
return ERROR_OK;
}
comparator_list[dwt_num].mask = mask;
comparator_list[dwt_num].function = watchpoint->rw + 5;
target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address, comparator_list[dwt_num].comp);
- target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x4, comparator_list[dwt_num].mask);
- target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x8, comparator_list[dwt_num].function);
+ target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x4, comparator_list[dwt_num].mask);
+ target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x8, comparator_list[dwt_num].function);
LOG_DEBUG("dwt_num %i 0x%" PRIx32 " 0x%" PRIx32 " 0x%" PRIx32 "", dwt_num, comparator_list[dwt_num].comp, comparator_list[dwt_num].mask, comparator_list[dwt_num].function);
}
else
{
- LOG_WARNING("Cannot watch data values"); /* Move this test to add_watchpoint */
+ /* Move this test to add_watchpoint */
+ LOG_WARNING("Cannot watch data values (id: %d)",
+ watchpoint->unique_id );
return ERROR_OK;
}
-
+ LOG_DEBUG("Watchpoint (ID: %d) address: 0x%08" PRIx32 " set=%d ",
+ watchpoint->unique_id, watchpoint->address, watchpoint->set );
return ERROR_OK;
}
if (!watchpoint->set)
{
- LOG_WARNING("watchpoint not set");
+ LOG_WARNING("watchpoint (wpid: %d) not set", watchpoint->unique_id );
return ERROR_OK;
}
+ LOG_DEBUG("Watchpoint (ID: %d) address: 0x%08" PRIx32 " set=%d ",
+ watchpoint->unique_id, watchpoint->address,watchpoint->set );
+
dwt_num = watchpoint->set - 1;
if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
}
comparator_list[dwt_num].used = 0;
comparator_list[dwt_num].function = 0;
- target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x8, comparator_list[dwt_num].function);
+ target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x8, comparator_list[dwt_num].function);
watchpoint->set = 0;
}
cortex_m3->dwt_comp_available--;
+ LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
return ERROR_OK;
}
}
cortex_m3->dwt_comp_available++;
+ LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
return ERROR_OK;
}
armv7m_common_t *armv7m = target->arch_info;
swjdp_common_t *swjdp = &armv7m->swjdp_info;
- if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP))
- {
+ /* NOTE: we "know" here that the register identifiers used
+ * in the v7m header match the Cortex-M3 Debug Core Register
+ * Selector values for R0..R15, xPSR, MSP, and PSP.
+ */
+ switch (num) {
+ case 0 ... 18:
/* read a normal core register */
retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
return ERROR_JTAG_DEVICE_ERROR;
}
LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",(int)num,*value);
- }
- else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
- {
- /* read other registers */
+ break;
+
+ case ARMV7M_PRIMASK:
+ case ARMV7M_BASEPRI:
+ case ARMV7M_FAULTMASK:
+ case ARMV7M_CONTROL:
+ /* Cortex-M3 packages these four registers as bitfields
+ * in one Debug Core register. So say r0 and r2 docs;
+ * it was removed from r1 docs, but still works.
+ */
cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
switch (num)
{
- case 19:
- *value = buf_get_u32((uint8_t*)value, 0, 8);
+ case ARMV7M_PRIMASK:
+ *value = buf_get_u32((uint8_t*)value, 0, 1);
break;
- case 20:
+ case ARMV7M_BASEPRI:
*value = buf_get_u32((uint8_t*)value, 8, 8);
break;
- case 21:
- *value = buf_get_u32((uint8_t*)value, 16, 8);
+ case ARMV7M_FAULTMASK:
+ *value = buf_get_u32((uint8_t*)value, 16, 1);
break;
- case 22:
- *value = buf_get_u32((uint8_t*)value, 24, 8);
+ case ARMV7M_CONTROL:
+ *value = buf_get_u32((uint8_t*)value, 24, 2);
break;
}
LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
- }
- else
- {
+ break;
+
+ default:
return ERROR_INVALID_ARGUMENTS;
}
* in "thumb" mode, or an INVSTATE exception will occur. This is a
* hack to deal with the fact that gdb will sometimes "forge"
* return addresses, and doesn't set the LSB correctly (i.e., when
- * printing expressions containing function calls, it sets LR=0.) */
-
- if (num == 14)
+ * printing expressions containing function calls, it sets LR = 0.)
+ * Valid exception return codes have bit 0 set too.
+ */
+ if (num == ARMV7M_R14)
value |= 0x01;
#endif
- if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP))
- {
+ /* NOTE: we "know" here that the register identifiers used
+ * in the v7m header match the Cortex-M3 Debug Core Register
+ * Selector values for R0..R15, xPSR, MSP, and PSP.
+ */
+ switch (num) {
+ case 0 ... 18:
retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
if (retval != ERROR_OK)
{
return ERROR_JTAG_DEVICE_ERROR;
}
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
- }
- else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
- {
- /* write other registers */
-
+ break;
+
+ case ARMV7M_PRIMASK:
+ case ARMV7M_BASEPRI:
+ case ARMV7M_FAULTMASK:
+ case ARMV7M_CONTROL:
+ /* Cortex-M3 packages these four registers as bitfields
+ * in one Debug Core register. So say r0 and r2 docs;
+ * it was removed from r1 docs, but still works.
+ */
cortexm3_dap_read_coreregister_u32(swjdp, ®, 20);
switch (num)
{
- case 19:
- buf_set_u32((uint8_t*)®, 0, 8, value);
+ case ARMV7M_PRIMASK:
+ buf_set_u32((uint8_t*)®, 0, 1, value);
break;
- case 20:
+ case ARMV7M_BASEPRI:
buf_set_u32((uint8_t*)®, 8, 8, value);
break;
- case 21:
- buf_set_u32((uint8_t*)®, 16, 8, value);
+ case ARMV7M_FAULTMASK:
+ buf_set_u32((uint8_t*)®, 16, 1, value);
break;
- case 22:
- buf_set_u32((uint8_t*)®, 24, 8, value);
+ case ARMV7M_CONTROL:
+ buf_set_u32((uint8_t*)®, 24, 2, value);
break;
}
cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
- }
- else
- {
+ break;
+
+ default:
return ERROR_INVALID_ARGUMENTS;
}
{
uint16_t dcrdr;
- mem_ap_read_buf_u16( swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
+ mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
*ctrl = (uint8_t)dcrdr;
*value = (uint8_t)(dcrdr >> 8);
if (dcrdr & (1 << 0))
{
dcrdr = 0;
- mem_ap_write_buf_u16( swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
+ mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
}
return ERROR_OK;
return ERROR_OK;
}
+/*
+ * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
+ * as at least ARM-1156T2. The interesting thing about Cortex-M is
+ * that *only* Thumb2 disassembly matters. There are also some small
+ * additions to Thumb2 that are specific to ARMv7-M.
+ */
+static int
+handle_cortex_m3_disassemble_command(struct command_context_s *cmd_ctx,
+ char *cmd, char **args, int argc)
+{
+ int retval = ERROR_OK;
+ target_t *target = get_current_target(cmd_ctx);
+ uint32_t address;
+ unsigned long count = 1;
+ arm_instruction_t cur_instruction;
+
+ errno = 0;
+ switch (argc) {
+ case 2:
+ count = strtoul(args[1], NULL, 0);
+ if (errno)
+ return ERROR_FAIL;
+ /* FALL THROUGH */
+ case 1:
+ address = strtoul(args[0], NULL, 0);
+ if (errno)
+ return ERROR_FAIL;
+ break;
+ default:
+ command_print(cmd_ctx,
+ "usage: cortex_m3 disassemble <address> [<count>]");
+ return ERROR_OK;
+ }
+
+ while (count--) {
+ retval = thumb2_opcode(target, address, &cur_instruction);
+ if (retval != ERROR_OK)
+ return retval;
+ command_print(cmd_ctx, "%s", cur_instruction.text);
+ address += cur_instruction.instruction_size;
+ }
+
+ return ERROR_OK;
+}
+
+static const struct {
+ char name[10];
+ unsigned mask;
+} vec_ids[] = {
+ { "hard_err", VC_HARDERR, },
+ { "int_err", VC_INTERR, },
+ { "bus_err", VC_BUSERR, },
+ { "state_err", VC_STATERR, },
+ { "chk_err", VC_CHKERR, },
+ { "nocp_err", VC_NOCPERR, },
+ { "mm_err", VC_MMERR, },
+ { "reset", VC_CORERESET, },
+};
+
+static int
+handle_cortex_m3_vector_catch_command(struct command_context_s *cmd_ctx,
+ char *cmd, char **argv, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ uint32_t demcr = 0;
+ int i;
+
+ mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+
+ if (argc > 0) {
+ unsigned catch = 0;
+
+ if (argc == 1) {
+ if (strcmp(argv[0], "all") == 0) {
+ catch = VC_HARDERR | VC_INTERR | VC_BUSERR
+ | VC_STATERR | VC_CHKERR | VC_NOCPERR
+ | VC_MMERR | VC_CORERESET;
+ goto write;
+ } else if (strcmp(argv[0], "none") == 0) {
+ goto write;
+ }
+ }
+ while (argc-- > 0) {
+ for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
+ if (strcmp(argv[argc], vec_ids[i].name) != 0)
+ continue;
+ catch |= vec_ids[i].mask;
+ break;
+ }
+ if (i == ARRAY_SIZE(vec_ids)) {
+ LOG_ERROR("No CM3 vector '%s'", argv[argc]);
+ return ERROR_INVALID_ARGUMENTS;
+ }
+ }
+write:
+ demcr &= ~0xffff;
+ demcr |= catch;
+
+ /* write, but don't assume it stuck */
+ mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
+ mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(vec_ids); i++)
+ command_print(cmd_ctx, "%9s: %s", vec_ids[i].name,
+ (demcr & vec_ids[i].mask) ? "catch" : "ignore");
+
+ return ERROR_OK;
+}
+
int cortex_m3_register_commands(struct command_context_s *cmd_ctx)
{
int retval;
retval = armv7m_register_commands(cmd_ctx);
- cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3", NULL, COMMAND_ANY, "cortex_m3 specific commands");
- register_command(cmd_ctx, cortex_m3_cmd, "maskisr", handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC, "mask cortex_m3 interrupts ['on'|'off']");
+ cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3",
+ NULL, COMMAND_ANY, "cortex_m3 specific commands");
+
+ register_command(cmd_ctx, cortex_m3_cmd, "disassemble",
+ handle_cortex_m3_disassemble_command, COMMAND_EXEC,
+ "disassemble Thumb2 instructions <address> [<count>]");
+ register_command(cmd_ctx, cortex_m3_cmd, "maskisr",
+ handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC,
+ "mask cortex_m3 interrupts ['on'|'off']");
+ register_command(cmd_ctx, cortex_m3_cmd, "vector_catch",
+ handle_cortex_m3_vector_catch_command, COMMAND_EXEC,
+ "catch hardware vectors ['all'|'none'|<list>]");
return retval;
}
{
if (!strcmp(args[0], "on"))
{
- cortex_m3_write_debug_halt_mask(target, C_HALT|C_MASKINTS, 0);
+ cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
}
else if (!strcmp(args[0], "off"))
{
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