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duan ellis target tcl work in progress
[openocd.git] / src / target / cortex_m3.c
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index ec3851667d386a380766b89af9e11397c21e34ff..dd9c6992536f4fb0d2b30c55464acd9aad3e28e1 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -47,11 +47,11 @@ void cortex_m3_enable_breakpoints(struct target_s *target);
 void cortex_m3_enable_watchpoints(struct target_s *target);
 int cortex_m3_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
 int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
-int cortex_m3_quit();
+int cortex_m3_quit(void);
 int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 *value);
 int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 value);
 int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer);
-int cortex_m3_examine(struct command_context_s *cmd_ctx, struct target_s *target);
+int cortex_m3_examine(struct target_s *target);
 
 #ifdef ARMV7_GDB_HACKS
 extern u8 armv7m_gdb_dummy_cpsr_value[];
@@ -81,6 +81,7 @@ target_type_t cortexm3_target =
        .write_memory = cortex_m3_write_memory,
        .bulk_write_memory = cortex_m3_bulk_write_memory,
        .checksum_memory = armv7m_checksum_memory,
+       .blank_check_memory = armv7m_blank_check_memory,
        
        .run_algorithm = armv7m_run_algorithm,
        
@@ -358,8 +359,10 @@ int cortex_m3_debug_entry(target_t *target)
                cortex_m3_examine_exception_reason(target);
        }
 
-       LOG_DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s", armv7m_mode_strings[armv7m->core_mode], \
-               *(u32*)(armv7m->core_cache->reg_list[15].value), target_state_strings[target->state]);
+       LOG_DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s", 
+                 armv7m_mode_strings[armv7m->core_mode],
+                 *(u32*)(armv7m->core_cache->reg_list[15].value), 
+                 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
 
        if (armv7m->post_debug_entry)
                armv7m->post_debug_entry(target);
@@ -435,7 +438,7 @@ int cortex_m3_poll(target_t *target)
 #if 0
     /* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script  */
        ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
-       LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, target_state_strings[target->state]);
+       LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, Jim_Nvp_value2name( nvp_target_state, target->state )->name );
 #endif
        
        return ERROR_OK;
@@ -448,7 +451,8 @@ int cortex_m3_halt(target_t *target)
        cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
        swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
        
-       LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
+       LOG_DEBUG("target->state: %s", 
+                 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
        
        if (target->state == TARGET_HALTED)
        {
@@ -522,7 +526,7 @@ int cortex_m3_soft_reset_halt(struct target_s *target)
                                LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%x, %i ms", dcb_dhcsr, timeout);
                }
                timeout++;
-               usleep(1000);
+               alive_sleep(1);
        }
                
        return ERROR_OK;
@@ -673,8 +677,10 @@ int cortex_m3_assert_reset(target_t *target)
        armv7m_common_t *armv7m = target->arch_info;
        cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
        swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+       int assert_srst = 1;
        
-       LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
+       LOG_DEBUG("target->state: %s", 
+                 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
        
        if (!(jtag_reset_config & RESET_HAS_SRST))
        {
@@ -689,7 +695,7 @@ int cortex_m3_assert_reset(target_t *target)
                
        ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 );
        
-       if (target->reset_mode == RESET_RUN)
+       if (!target->reset_halt)
        {
                /* Set/Clear C_MASKINTS in a separate operation */
                if (cortex_m3->dcb_dhcsr & C_MASKINTS)
@@ -712,12 +718,33 @@ int cortex_m3_assert_reset(target_t *target)
                
        if (strcmp(cortex_m3->variant, "lm3s") == 0)
        {
-               /* this causes the luminary device to reset using the watchdog */
-               ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ );
-               LOG_DEBUG("Using Luminary Reset: SYSRESETREQ");
+               /* get revision of lm3s target, only early silicon has this issue
+                * Fury Rev B, DustDevil Rev B, Tempest all ok */
+               
+               u32 did0;
+               
+               if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
+               {
+                       switch ((did0 >> 16) & 0xff)
+                       {
+                               case 0:
+                                       /* all Sandstorm suffer issue */
+                                       assert_srst = 0;
+                                       break;
+                               
+                               case 1:
+                               case 3:
+                                       /* only Fury/DustDevil rev A suffer reset problems */
+                                       if (((did0 >> 8) & 0xff) == 0)
+                                               assert_srst = 0;
+                                       break;
+                       }
+               }
        }
-       else
+       
+       if (assert_srst)
        {
+               /* default to asserting srst */
                if (jtag_reset_config & RESET_SRST_PULLS_TRST)
                {
                        jtag_add_reset(1, 1);
@@ -727,18 +754,32 @@ int cortex_m3_assert_reset(target_t *target)
                        jtag_add_reset(0, 1);
                }
        }
+       else
+       {
+               /* this causes the luminary device to reset using the watchdog */
+               ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ );
+               LOG_DEBUG("Using Luminary Reset: SYSRESETREQ");
+       }
        
        target->state = TARGET_RESET;
        jtag_add_sleep(50000);
        
        armv7m_invalidate_core_regs(target);
 
+    if (target->reset_halt)
+    {
+       int retval;
+               if ((retval = target_halt(target))!=ERROR_OK)
+                       return retval;
+    }
+       
        return ERROR_OK;
 }
 
 int cortex_m3_deassert_reset(target_t *target)
 {              
-       LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
+       LOG_DEBUG("target->state: %s", 
+                 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
        
        /* deassert reset lines */
        jtag_add_reset(0, 0);
@@ -1278,7 +1319,7 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta
        return ERROR_OK;
 }
 
-int cortex_m3_examine(struct command_context_s *cmd_ctx, struct target_s *target)
+int cortex_m3_examine(struct target_s *target)
 {
        int retval;
        u32 cpuid, fpcr, dwtcr, ictr;
@@ -1338,8 +1379,7 @@ int cortex_m3_examine(struct command_context_s *cmd_ctx, struct target_s *target
        return ERROR_OK;
 }
 
-
-int cortex_m3_quit()
+int cortex_m3_quit(void)
 {
        
        return ERROR_OK;
@@ -1490,7 +1530,6 @@ int cortex_m3_target_command(struct command_context_s *cmd_ctx, char *cmd, char
                variant = args[4];
        
        cortex_m3_init_arch_info(target, cortex_m3, chain_pos, variant);
-       cortex_m3_register_commands(cmd_ctx);
        
        return ERROR_OK;
 }
@@ -1503,4 +1542,3 @@ int cortex_m3_register_commands(struct command_context_s *cmd_ctx)
        
        return retval;
 }
-
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