/* Make sure we are in Thumb mode */
buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
- buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1<<24));
+ buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
}
return ERROR_OK;
}
-/* int irqstepcount=0; */
+/* int irqstepcount = 0; */
int cortex_m3_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
{
/* get pointers to arch-specific information */
int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval;
- int fp_num=0;
+ int fp_num = 0;
uint32_t hilo;
/* get pointers to arch-specific information */
int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
- int dwt_num=0;
+ int dwt_num = 0;
uint32_t mask, temp;
/* get pointers to arch-specific information */
* in "thumb" mode, or an INVSTATE exception will occur. This is a
* hack to deal with the fact that gdb will sometimes "forge"
* return addresses, and doesn't set the LSB correctly (i.e., when
- * printing expressions containing function calls, it sets LR=0.) */
+ * printing expressions containing function calls, it sets LR = 0.) */
if (num == 14)
value |= 0x01;
armv7m->swjdp_info.ap_tar_value = -1;
armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
armv7m->swjdp_info.memaccess_tck = 8;
- armv7m->swjdp_info.tar_autoincr_block = (1<<12); /* Cortex-M3 has 4096 bytes autoincrement range */
+ armv7m->swjdp_info.tar_autoincr_block = (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */
/* initialize arch-specific breakpoint handling */