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- Fixes '=' whitespace
[openocd.git] / src / target / cortex_m3.c
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 40aadea2ed2bc0baa30baacca19ae015d3b90c77..c1ebae3f10eede1c4f39aa7005dd2a3a0d73a9af 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -46,13 +46,13 @@ void cortex_m3_enable_watchpoints(struct target_s *target);
 int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp);
 int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 int cortex_m3_quit(void);
-int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 *value);
-int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 value);
-int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer);
+int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type, uint32_t num, uint32_t *value);
+int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type, uint32_t num, uint32_t value);
+int cortex_m3_target_request_data(target_t *target, uint32_t size, uint8_t *buffer);
 int cortex_m3_examine(struct target_s *target);
 
 #ifdef ARMV7_GDB_HACKS
-extern u8 armv7m_gdb_dummy_cpsr_value[];
+extern uint8_t armv7m_gdb_dummy_cpsr_value[];
 extern reg_t armv7m_gdb_dummy_cpsr_reg;
 #endif
 
@@ -95,10 +95,10 @@ target_type_t cortexm3_target =
        .quit = cortex_m3_quit
 };
 
-int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
+int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, uint32_t *value, int regnum)
 {
        int retval;
-       u32 dcrdr;
+       uint32_t dcrdr;
 
        /* because the DCB_DCRDR is used for the emulated dcc channel
         * we gave to save/restore the DCB_DCRDR when used */
@@ -120,10 +120,10 @@ int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int re
        return retval;
 }
 
-int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
+int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, uint32_t value, int regnum)
 {
        int retval;
-       u32 dcrdr;
+       uint32_t dcrdr;
 
        /* because the DCB_DCRDR is used for the emulated dcc channel
         * we gave to save/restore the DCB_DCRDR when used */
@@ -146,7 +146,7 @@ int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int re
 }
 
 
-int cortex_m3_write_debug_halt_mask(target_t *target, u32 mask_on, u32 mask_off)
+int cortex_m3_write_debug_halt_mask(target_t *target, uint32_t mask_on, uint32_t mask_off)
 {
        /* get pointers to arch-specific information */
        armv7m_common_t *armv7m = target->arch_info;
@@ -175,7 +175,7 @@ int cortex_m3_clear_halt(target_t *target)
        mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
        /* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */
        mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
-       LOG_DEBUG(" NVIC_DFSR 0x%x", cortex_m3->nvic_dfsr);
+       LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
 
        return ERROR_OK;
 }
@@ -186,7 +186,7 @@ int cortex_m3_single_step_core(target_t *target)
        armv7m_common_t *armv7m = target->arch_info;
        cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
        swjdp_common_t *swjdp = &armv7m->swjdp_info;
-       u32 dhcsr_save;
+       uint32_t dhcsr_save;
 
        /* backup dhcsr reg */
        dhcsr_save = cortex_m3->dcb_dhcsr;
@@ -204,12 +204,12 @@ int cortex_m3_single_step_core(target_t *target)
        return ERROR_OK;
 }
 
-int cortex_m3_exec_opcode(target_t *target,u32 opcode, int len /* MODE, r0_invalue, &r0_outvalue */ )
+int cortex_m3_exec_opcode(target_t *target,uint32_t opcode, int len /* MODE, r0_invalue, &r0_outvalue */ )
 {
        /* get pointers to arch-specific information */
        armv7m_common_t *armv7m = target->arch_info;
        swjdp_common_t *swjdp = &armv7m->swjdp_info;
-       u32 savedram;
+       uint32_t savedram;
        int retvalue;
 
        mem_ap_read_u32(swjdp, 0x20000000, &savedram);
@@ -224,13 +224,13 @@ int cortex_m3_exec_opcode(target_t *target,u32 opcode, int len /* MODE, r0_inval
 
 #if 0
 /* Enable interrupts */
-int cortex_m3_cpsie(target_t *target, u32 IF)
+int cortex_m3_cpsie(target_t *target, uint32_t IF)
 {
        return cortex_m3_exec_opcode(target, ARMV7M_T_CPSIE(IF), 2);
 }
 
 /* Disable interrupts */
-int cortex_m3_cpsid(target_t *target, u32 IF)
+int cortex_m3_cpsid(target_t *target, uint32_t IF)
 {
        return cortex_m3_exec_opcode(target, ARMV7M_T_CPSID(IF), 2);
 }
@@ -239,7 +239,7 @@ int cortex_m3_cpsid(target_t *target, u32 IF)
 int cortex_m3_endreset_event(target_t *target)
 {
        int i;
-       u32 dcb_demcr;
+       uint32_t dcb_demcr;
 
        /* get pointers to arch-specific information */
        armv7m_common_t *armv7m = target->arch_info;
@@ -249,7 +249,7 @@ int cortex_m3_endreset_event(target_t *target)
        cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list;
 
        mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
-       LOG_DEBUG("DCB_DEMCR = 0x%8.8x",dcb_demcr);
+       LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
 
        /* this regsiter is used for emulated dcc channel */
        mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
@@ -323,7 +323,7 @@ int cortex_m3_examine_debug_reason(target_t *target)
 
 int cortex_m3_examine_exception_reason(target_t *target)
 {
-       u32 shcsr, except_sr, cfsr = -1, except_ar = -1;
+       uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
 
        /* get pointers to arch-specific information */
        armv7m_common_t *armv7m = target->arch_info;
@@ -366,7 +366,7 @@ int cortex_m3_examine_exception_reason(target_t *target)
                        break;
        }
        swjdp_transaction_endcheck(swjdp);
-       LOG_DEBUG("%s SHCSR 0x%x, SR 0x%x, CFSR 0x%x, AR 0x%x", armv7m_exception_string(armv7m->exception_number), \
+       LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \
                shcsr, except_sr, cfsr, except_ar);
        return ERROR_OK;
 }
@@ -374,7 +374,7 @@ int cortex_m3_examine_exception_reason(target_t *target)
 int cortex_m3_debug_entry(target_t *target)
 {
        int i;
-       u32 xPSR;
+       uint32_t xPSR;
        int retval;
 
        /* get pointers to arch-specific information */
@@ -441,9 +441,9 @@ int cortex_m3_debug_entry(target_t *target)
                cortex_m3_examine_exception_reason(target);
        }
 
-       LOG_DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s",
+       LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
                armv7m_mode_strings[armv7m->core_mode],
-               *(u32*)(armv7m->core_cache->reg_list[15].value),
+               *(uint32_t*)(armv7m->core_cache->reg_list[15].value),
                Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
 
        if (armv7m->post_debug_entry)
@@ -485,7 +485,7 @@ int cortex_m3_poll(target_t *target)
        if (target->state == TARGET_RESET)
        {
                /* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */
-               LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%x", cortex_m3->dcb_dhcsr);
+               LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32 "", cortex_m3->dcb_dhcsr);
                cortex_m3_endreset_event(target);
                target->state = TARGET_RUNNING;
                prev_target_state = TARGET_RUNNING;
@@ -544,7 +544,7 @@ int cortex_m3_halt(target_t *target)
 
        if (target->state == TARGET_RESET)
        {
-               if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
+               if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
                {
                        LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
                        return ERROR_TARGET_FAILURE;
@@ -574,7 +574,7 @@ int cortex_m3_soft_reset_halt(struct target_s *target)
        armv7m_common_t *armv7m = target->arch_info;
        cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
        swjdp_common_t *swjdp = &armv7m->swjdp_info;
-       u32 dcb_dhcsr = 0;
+       uint32_t dcb_dhcsr = 0;
        int retval, timeout = 0;
 
        /* Enter debug state on reset, cf. end_reset_event() */
@@ -595,12 +595,12 @@ int cortex_m3_soft_reset_halt(struct target_s *target)
                        mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
                        if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
                        {
-                               LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%x, nvic_dfsr 0x%x", dcb_dhcsr, cortex_m3->nvic_dfsr);
+                               LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%" PRIx32 ", nvic_dfsr 0x%" PRIx32 "", dcb_dhcsr, cortex_m3->nvic_dfsr);
                                cortex_m3_poll(target);
                                return ERROR_OK;
                        }
                        else
-                               LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%x, %i ms", dcb_dhcsr, timeout);
+                               LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%" PRIx32 ", %i ms", dcb_dhcsr, timeout);
                }
                timeout++;
                alive_sleep(1);
@@ -609,12 +609,12 @@ int cortex_m3_soft_reset_halt(struct target_s *target)
        return ERROR_OK;
 }
 
-int cortex_m3_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
+int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
 {
        /* get pointers to arch-specific information */
        armv7m_common_t *armv7m = target->arch_info;
        breakpoint_t *breakpoint = NULL;
-       u32 resume_pc;
+       uint32_t resume_pc;
 
        if (target->state != TARGET_HALTED)
        {
@@ -641,7 +641,7 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand
 
                /* Make sure we are in Thumb mode */
                buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
-                       buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1<<24));
+                       buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
                armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
                armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
        }
@@ -664,7 +664,7 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand
                /* Single step past breakpoint at current address */
                if ((breakpoint = breakpoint_find(target, resume_pc)))
                {
-                       LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
+                       LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
                        cortex_m3_unset_breakpoint(target, breakpoint);
                        cortex_m3_single_step_core(target);
                        cortex_m3_set_breakpoint(target, breakpoint);
@@ -682,20 +682,20 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand
        {
                target->state = TARGET_RUNNING;
                target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
-               LOG_DEBUG("target resumed at 0x%x", resume_pc);
+               LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
        }
        else
        {
                target->state = TARGET_DEBUG_RUNNING;
                target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
-               LOG_DEBUG("target debug resumed at 0x%x", resume_pc);
+               LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
        }
 
        return ERROR_OK;
 }
 
-/* int irqstepcount=0; */
-int cortex_m3_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
+/* int irqstepcount = 0; */
+int cortex_m3_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
 {
        /* get pointers to arch-specific information */
        armv7m_common_t *armv7m = target->arch_info;
@@ -734,12 +734,12 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle
        if (breakpoint)
                cortex_m3_set_breakpoint(target, breakpoint);
 
-       LOG_DEBUG("target stepped dcb_dhcsr = 0x%x nvic_icsr = 0x%x", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
+       LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 
        cortex_m3_debug_entry(target);
        target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 
-       LOG_DEBUG("target stepped dcb_dhcsr = 0x%x nvic_icsr = 0x%x", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
+       LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
        return ERROR_OK;
 }
 
@@ -753,6 +753,7 @@ int cortex_m3_assert_reset(target_t *target)
        LOG_DEBUG("target->state: %s",
                Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
 
+       enum reset_types jtag_reset_config = jtag_get_reset_config();
        if (!(jtag_reset_config & RESET_HAS_SRST))
        {
                LOG_ERROR("Can't assert SRST");
@@ -796,7 +797,7 @@ int cortex_m3_assert_reset(target_t *target)
                /* get revision of lm3s target, only early silicon has this issue
                 * Fury Rev B, DustDevil Rev B, Tempest all ok */
 
-               u32 did0;
+               uint32_t did0;
 
                if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
                {
@@ -838,7 +839,7 @@ int cortex_m3_assert_reset(target_t *target)
                {
                        /* I do not know why this is necessary, but it fixes strange effects
                         * (step/resume cause a NMI after reset) on LM3S6918 -- Michael Schwingen */
-                       u32 tmp;
+                       uint32_t tmp;
                        mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
                }
        }
@@ -851,7 +852,7 @@ int cortex_m3_assert_reset(target_t *target)
        if (target->reset_halt)
        {
                int retval;
-               if ((retval = target_halt(target))!=ERROR_OK)
+               if ((retval = target_halt(target)) != ERROR_OK)
                        return retval;
        }
 
@@ -885,8 +886,8 @@ void cortex_m3_enable_breakpoints(struct target_s *target)
 int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
        int retval;
-       int fp_num=0;
-       u32 hilo;
+       int fp_num = 0;
+       uint32_t hilo;
 
        /* get pointers to arch-specific information */
        armv7m_common_t *armv7m = target->arch_info;
@@ -907,7 +908,7 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 
        if (breakpoint->type == BKPT_HARD)
        {
-               while(comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
+               while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
                        fp_num++;
                if (fp_num >= cortex_m3->fp_num_code)
                {
@@ -920,7 +921,7 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                comparator_list[fp_num].used = 1;
                comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
                target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
-               LOG_DEBUG("fpc_num %i fpcr_value 0x%x", fp_num, comparator_list[fp_num].fpcr_value);
+               LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
                if (!cortex_m3->fpb_enabled)
                {
                        LOG_DEBUG("FPB wasn't enabled, do it now");
@@ -929,13 +930,13 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
        }
        else if (breakpoint->type == BKPT_SOFT)
        {
-               u8 code[4];
+               uint8_t code[4];
                buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11));
-               if((retval = target_read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
+               if ((retval = target_read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
                {
                        return retval;
                }
-               if((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK)
+               if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK)
                {
                        return retval;
                }
@@ -976,14 +977,14 @@ int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint
                /* restore original instruction (kept in target endianness) */
                if (breakpoint->length == 4)
                {
-                       if((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
+                       if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
                        {
                                return retval;
                        }
                }
                else
                {
-                       if((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
+                       if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
                        {
                                return retval;
                        }
@@ -1074,8 +1075,8 @@ int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin
 
 int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 {
-       int dwt_num=0;
-       u32 mask, temp;
+       int dwt_num = 0;
+       uint32_t mask, temp;
 
        /* get pointers to arch-specific information */
        armv7m_common_t *armv7m = target->arch_info;
@@ -1090,7 +1091,7 @@ int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 
        if (watchpoint->mask == 0xffffffffu)
        {
-               while(comparator_list[dwt_num].used && (dwt_num < cortex_m3->dwt_num_comp))
+               while (comparator_list[dwt_num].used && (dwt_num < cortex_m3->dwt_num_comp))
                        dwt_num++;
                if (dwt_num >= cortex_m3->dwt_num_comp)
                {
@@ -1113,7 +1114,7 @@ int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
                target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address, comparator_list[dwt_num].comp);
                target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x4, comparator_list[dwt_num].mask);
                target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x8, comparator_list[dwt_num].function);
-               LOG_DEBUG("dwt_num %i 0x%x 0x%x 0x%x", dwt_num, comparator_list[dwt_num].comp, comparator_list[dwt_num].mask, comparator_list[dwt_num].function);
+               LOG_DEBUG("dwt_num %i 0x%" PRIx32 " 0x%" PRIx32 " 0x%" PRIx32 "", dwt_num, comparator_list[dwt_num].comp, comparator_list[dwt_num].mask, comparator_list[dwt_num].function);
        }
        else
        {
@@ -1217,7 +1218,7 @@ void cortex_m3_enable_watchpoints(struct target_s *target)
        }
 }
 
-int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype type, u32 num, u32 * value)
+int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t * value)
 {
        int retval;
        /* get pointers to arch-specific information */
@@ -1234,7 +1235,7 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ
                        LOG_ERROR("JTAG failure %i",retval);
                        return ERROR_JTAG_DEVICE_ERROR;
                }
-               LOG_DEBUG("load from core reg %i  value 0x%x",num,*value);
+               LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "",(int)num,*value);
        }
        else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
        {
@@ -1244,23 +1245,23 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ
                switch (num)
                {
                        case 19:
-                               *value = buf_get_u32((u8*)value, 0, 8);
+                               *value = buf_get_u32((uint8_t*)value, 0, 8);
                                break;
 
                        case 20:
-                               *value = buf_get_u32((u8*)value, 8, 8);
+                               *value = buf_get_u32((uint8_t*)value, 8, 8);
                                break;
 
                        case 21:
-                               *value = buf_get_u32((u8*)value, 16, 8);
+                               *value = buf_get_u32((uint8_t*)value, 16, 8);
                                break;
 
                        case 22:
-                               *value = buf_get_u32((u8*)value, 24, 8);
+                               *value = buf_get_u32((uint8_t*)value, 24, 8);
                                break;
                }
 
-               LOG_DEBUG("load from special reg %i value 0x%x", num, *value);
+               LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
        }
        else
        {
@@ -1270,10 +1271,10 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ
        return ERROR_OK;
 }
 
-int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype type, u32 num, u32 value)
+int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t value)
 {
        int retval;
-       u32 reg;
+       uint32_t reg;
 
        /* get pointers to arch-specific information */
        armv7m_common_t *armv7m = target->arch_info;
@@ -1284,7 +1285,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty
         * in "thumb" mode, or an INVSTATE exception will occur. This is a
         * hack to deal with the fact that gdb will sometimes "forge"
         * return addresses, and doesn't set the LSB correctly (i.e., when
-        * printing expressions containing function calls, it sets LR=0.) */
+        * printing expressions containing function calls, it sets LR = 0.) */
 
        if (num == 14)
                value |= 0x01;
@@ -1299,7 +1300,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty
                        armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
                        return ERROR_JTAG_DEVICE_ERROR;
                }
-               LOG_DEBUG("write core reg %i value 0x%x", num, value);
+               LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
        }
        else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
        {
@@ -1310,25 +1311,25 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty
                switch (num)
                {
                        case 19:
-                               buf_set_u32((u8*)&reg, 0, 8, value);
+                               buf_set_u32((uint8_t*)&reg, 0, 8, value);
                                break;
 
                        case 20:
-                               buf_set_u32((u8*)&reg, 8, 8, value);
+                               buf_set_u32((uint8_t*)&reg, 8, 8, value);
                                break;
 
                        case 21:
-                               buf_set_u32((u8*)&reg, 16, 8, value);
+                               buf_set_u32((uint8_t*)&reg, 16, 8, value);
                                break;
 
                        case 22:
-                               buf_set_u32((u8*)&reg, 24, 8, value);
+                               buf_set_u32((uint8_t*)&reg, 24, 8, value);
                                break;
                }
 
                cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
 
-               LOG_DEBUG("write special reg %i value 0x%x ", num, value);
+               LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
        }
        else
        {
@@ -1338,7 +1339,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty
        return ERROR_OK;
 }
 
-int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int cortex_m3_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
        /* get pointers to arch-specific information */
        armv7m_common_t *armv7m = target->arch_info;
@@ -1370,7 +1371,7 @@ int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 co
        return retval;
 }
 
-int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int cortex_m3_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
        /* get pointers to arch-specific information */
        armv7m_common_t *armv7m = target->arch_info;
@@ -1400,7 +1401,7 @@ int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 c
        return retval;
 }
 
-int cortex_m3_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
+int cortex_m3_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
 {
        return cortex_m3_write_memory(target, address, 4, count, buffer);
 }
@@ -1419,7 +1420,7 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta
 int cortex_m3_examine(struct target_s *target)
 {
        int retval;
-       u32 cpuid, fpcr, dwtcr, ictr;
+       uint32_t cpuid, fpcr, dwtcr, ictr;
        int i;
 
        /* get pointers to arch-specific information */
@@ -1440,7 +1441,7 @@ int cortex_m3_examine(struct target_s *target)
 
                if (((cpuid >> 4) & 0xc3f) == 0xc23)
                        LOG_DEBUG("CORTEX-M3 processor detected");
-               LOG_DEBUG("cpuid: 0x%8.8x", cpuid);
+               LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
 
                target_read_u32(target, NVIC_ICTR, &ictr);
                cortex_m3->intlinesnum = (ictr & 0x1F) + 1;
@@ -1448,7 +1449,7 @@ int cortex_m3_examine(struct target_s *target)
                for (i = 0; i < cortex_m3->intlinesnum; i++)
                {
                        target_read_u32(target, NVIC_ISE0 + 4 * i, cortex_m3->intsetenable + i);
-                       LOG_DEBUG("interrupt enable[%i] = 0x%8.8x", i, cortex_m3->intsetenable[i]);
+                       LOG_DEBUG("interrupt enable[%i] = 0x%8.8" PRIx32 "", i, cortex_m3->intsetenable[i]);
                }
 
                /* Setup FPB */
@@ -1464,7 +1465,7 @@ int cortex_m3_examine(struct target_s *target)
                        cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
                        cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
                }
-               LOG_DEBUG("FPB fpcr 0x%x, numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
+               LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
 
                /* Setup DWT */
                target_read_u32(target, DWT_CTRL, &dwtcr);
@@ -1486,13 +1487,13 @@ int cortex_m3_quit(void)
        return ERROR_OK;
 }
 
-int cortex_m3_dcc_read(swjdp_common_t *swjdp, u8 *value, u8 *ctrl)
+int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl)
 {
-       u16 dcrdr;
+       uint16_t dcrdr;
 
-       mem_ap_read_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
-       *ctrl = (u8)dcrdr;
-       *value = (u8)(dcrdr >> 8);
+       mem_ap_read_buf_u16( swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
+       *ctrl = (uint8_t)dcrdr;
+       *value = (uint8_t)(dcrdr >> 8);
 
        LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
 
@@ -1501,19 +1502,19 @@ int cortex_m3_dcc_read(swjdp_common_t *swjdp, u8 *value, u8 *ctrl)
        if (dcrdr & (1 << 0))
        {
                dcrdr = 0;
-               mem_ap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
+               mem_ap_write_buf_u16( swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
        }
 
        return ERROR_OK;
 }
 
-int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer)
+int cortex_m3_target_request_data(target_t *target, uint32_t size, uint8_t *buffer)
 {
        armv7m_common_t *armv7m = target->arch_info;
        swjdp_common_t *swjdp = &armv7m->swjdp_info;
-       u8 data;
-       u8 ctrl;
-       u32 i;
+       uint8_t data;
+       uint8_t ctrl;
+       uint32_t i;
 
        for (i = 0; i < (size * 4); i++)
        {
@@ -1537,15 +1538,15 @@ int cortex_m3_handle_target_request(void *priv)
 
        if (target->state == TARGET_RUNNING)
        {
-               u8 data;
-               u8 ctrl;
+               uint8_t data;
+               uint8_t ctrl;
 
                cortex_m3_dcc_read(swjdp, &data, &ctrl);
 
                /* check if we have data */
                if (ctrl & (1 << 0))
                {
-                       u32 request;
+                       uint32_t request;
 
                        /* we assume target is quick enough */
                        request = data;
@@ -1579,6 +1580,7 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jt
        armv7m->swjdp_info.ap_tar_value = -1;
        armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
        armv7m->swjdp_info.memaccess_tck = 8;
+       armv7m->swjdp_info.tar_autoincr_block = (1 << 12);      /* Cortex-M3 has 4096 bytes autoincrement range */
 
        /* initialize arch-specific breakpoint handling */
 
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