Michael Bruck:

[openocd.git] / src / target / cortex_m3.c

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 8e8665bc44c4ec4b8cbf4e71981133379c949955..964c6b8c397687645f734f97bdab062bb0d0a5fd 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -639,7 +639,7 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand
        return ERROR_OK;
 }
 
-//int irqstepcount=0;
+/* int irqstepcount=0; */
 int cortex_m3_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
 {
        /* get pointers to arch-specific information */
@@ -1134,7 +1134,7 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ
                        ERROR("JTAG failure %i",retval);
                        return ERROR_JTAG_DEVICE_ERROR;
                }
-               //DEBUG("load from core reg %i  value 0x%x",num,*value);
+               /* DEBUG("load from core reg %i  value 0x%x",num,*value); */
        }
        else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
        {
@@ -1372,8 +1372,12 @@ int cortex_m3_dcc_read(swjdp_common_t *swjdp, u8 *value, u8 *ctrl)
        
        /* write ack back to software dcc register
         * signify we have read data */
-       dcrdr = 0;
-       ahbap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
+       if (dcrdr & (1 << 0))
+       {
+               dcrdr = 0;
+               ahbap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
+       }
+       
        return ERROR_OK;
 }
 
@@ -1413,10 +1417,11 @@ int cortex_m3_handle_target_request(void *priv)
                cortex_m3_dcc_read(swjdp, &data, &ctrl);
                
                /* check if we have data */
-               if (ctrl & (1<<0))
+               if (ctrl & (1 << 0))
                {
                        u32 request;
                        
+                       /* we assume target is quick enough */
                        request = data;
                        cortex_m3_dcc_read(swjdp, &data, &ctrl);
                        request |= (data << 8);
@@ -1463,7 +1468,7 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, in
        armv7m->arch_info = cortex_m3;
        armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
        armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
-//     armv7m->full_context = cortex_m3_full_context;
+       /* armv7m->full_context = cortex_m3_full_context; */
        
        target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
        
@@ -1476,6 +1481,7 @@ int cortex_m3_target_command(struct command_context_s *cmd_ctx, char *cmd, char
        int chain_pos;
        char *variant = NULL;
        cortex_m3_common_t *cortex_m3 = malloc(sizeof(cortex_m3_common_t));
+       memset(cortex_m3, 0, sizeof(*cortex_m3));
 
        if (argc < 4)
        {