extern reg_t armv7m_gdb_dummy_cpsr_reg;
#endif
-static int cortex_m3_has_mmu(struct target_s *target, bool *has_mmu)
-{
- *has_mmu = false;
- return ERROR_OK;
-}
-
static int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp,
uint32_t *value, int regnum)
{
*register_get_last_cache_p(&target->reg_cache) = cache;
cm3->dwt_cache = cache;
- LOG_INFO("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
+ LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
dwtcr, cm3->dwt_num_comp,
(dwtcr & (0xf << 24)) ? " only" : "/trigger");
static int
handle_cortex_m3_vector_catch_command(struct command_context_s *cmd_ctx,
- char *cmd, char **argv, int argc)
+ char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
unsigned catch = 0;
if (argc == 1) {
- if (strcmp(argv[0], "all") == 0) {
+ if (strcmp(args[0], "all") == 0) {
catch = VC_HARDERR | VC_INTERR | VC_BUSERR
| VC_STATERR | VC_CHKERR | VC_NOCPERR
| VC_MMERR | VC_CORERESET;
goto write;
- } else if (strcmp(argv[0], "none") == 0) {
+ } else if (strcmp(args[0], "none") == 0) {
goto write;
}
}
while (argc-- > 0) {
for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
- if (strcmp(argv[argc], vec_ids[i].name) != 0)
+ if (strcmp(args[argc], vec_ids[i].name) != 0)
continue;
catch |= vec_ids[i].mask;
break;
}
if (i == ARRAY_SIZE(vec_ids)) {
- LOG_ERROR("No CM3 vector '%s'", argv[argc]);
+ LOG_ERROR("No CM3 vector '%s'", args[argc]);
return ERROR_INVALID_ARGUMENTS;
}
}
.register_commands = cortex_m3_register_commands,
.target_create = cortex_m3_target_create,
.init_target = cortex_m3_init_target,
- .has_mmu = cortex_m3_has_mmu,
.examine = cortex_m3_examine,
};