embedded hosts: optimize common code path for core arm operations

[openocd.git] / src / target / cortex_m3.c

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index be81af98a1644977f8b7aab42be3e7125df10b4c..6bc427a4389beb4cdf2281bb4bc2883f0eccec23 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -37,6 +37,7 @@
 #include "target_type.h"
 #include "arm_disassembler.h"
 #include "register.h"
+#include "arm_opcodes.h"
 
 
 /* NOTE:  most of this should work fine for the Cortex-M1 and
@@ -51,11 +52,6 @@ static void cortex_m3_enable_watchpoints(struct target *target);
 static int cortex_m3_store_core_reg_u32(struct target *target,
                enum armv7m_regtype type, uint32_t num, uint32_t value);
 
-#ifdef ARMV7_GDB_HACKS
-extern uint8_t armv7m_gdb_dummy_cpsr_value[];
-extern struct reg armv7m_gdb_dummy_cpsr_reg;
-#endif
-
 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
                uint32_t *value, int regnum)
 {
@@ -880,7 +876,7 @@ cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
        else if (breakpoint->type == BKPT_SOFT)
        {
                uint8_t code[4];
-               buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11));
+               buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
                if ((retval = target_read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
                {
                        return retval;
@@ -1141,13 +1137,6 @@ cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 {
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 
-       /* REVISIT why check? DWT can be updated with core running ... */
-       if (target->state != TARGET_HALTED)
-       {
-               LOG_WARNING("target not halted");
-               return ERROR_TARGET_NOT_HALTED;
-       }
-
        if (cortex_m3->dwt_comp_available < 1)
        {
                LOG_DEBUG("no comparators?");
@@ -1614,6 +1603,12 @@ static int cortex_m3_examine(struct target *target)
 
                /* Setup DWT */
                cortex_m3_dwt_setup(cortex_m3, target);
+
+               /* These hardware breakpoints only work for code in flash! */
+               LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
+                               target_name(target),
+                               cortex_m3->fp_num_code,
+                               cortex_m3->dwt_num_comp);
        }
 
        return ERROR_OK;
@@ -1937,6 +1932,9 @@ static const struct command_registration cortex_m3_exec_command_handlers[] = {
        COMMAND_REGISTRATION_DONE
 };
 static const struct command_registration cortex_m3_command_handlers[] = {
+       {
+               .chain = armv7m_command_handlers,
+       },
        {
                .name = "cortex_m3",
                .mode = COMMAND_ANY,
@@ -1946,12 +1944,6 @@ static const struct command_registration cortex_m3_command_handlers[] = {
        COMMAND_REGISTRATION_DONE
 };
 
-static int cortex_m3_register_commands(struct command_context *cmd_ctx)
-{
-       armv7m_register_commands(cmd_ctx);
-       return register_commands(cmd_ctx, NULL, cortex_m3_command_handlers);
-}
-
 struct target_type cortexm3_target =
 {
        .name = "cortex_m3",
@@ -1984,7 +1976,7 @@ struct target_type cortexm3_target =
        .add_watchpoint = cortex_m3_add_watchpoint,
        .remove_watchpoint = cortex_m3_remove_watchpoint,
 
-       .register_commands = cortex_m3_register_commands,
+       .commands = cortex_m3_command_handlers,
        .target_create = cortex_m3_target_create,
        .init_target = cortex_m3_init_target,
        .examine = cortex_m3_examine,