Comment and doxygen fixes

[openocd.git] / src / target / cortex_m3.c

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 195a3b9ad5b554df990b89f4bd05d3ea7de73873..6bc427a4389beb4cdf2281bb4bc2883f0eccec23 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -37,6 +37,7 @@
 #include "target_type.h"
 #include "arm_disassembler.h"
 #include "register.h"
+#include "arm_opcodes.h"
 
 
 /* NOTE:  most of this should work fine for the Cortex-M1 and
@@ -51,11 +52,6 @@ static void cortex_m3_enable_watchpoints(struct target *target);
 static int cortex_m3_store_core_reg_u32(struct target *target,
                enum armv7m_regtype type, uint32_t num, uint32_t value);
 
-#ifdef ARMV7_GDB_HACKS
-extern uint8_t armv7m_gdb_dummy_cpsr_value[];
-extern struct reg armv7m_gdb_dummy_cpsr_reg;
-#endif
-
 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
                uint32_t *value, int regnum)
 {
@@ -880,7 +876,7 @@ cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
        else if (breakpoint->type == BKPT_SOFT)
        {
                uint8_t code[4];
-               buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11));
+               buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
                if ((retval = target_read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
                {
                        return retval;
@@ -1607,6 +1603,12 @@ static int cortex_m3_examine(struct target *target)
 
                /* Setup DWT */
                cortex_m3_dwt_setup(cortex_m3, target);
+
+               /* These hardware breakpoints only work for code in flash! */
+               LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
+                               target_name(target),
+                               cortex_m3->fp_num_code,
+                               cortex_m3->dwt_num_comp);
        }
 
        return ERROR_OK;