+ struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target);
+ struct swjdp_common_s *swjdp = &cortex_m3->armv7m.swjdp_info;
+ int assert_srst = 1;
+
+ LOG_DEBUG("target->state: %s",
+ target_state_name(target));
+
+ enum reset_types jtag_reset_config = jtag_get_reset_config();
+
+ /*
+ * We can reset Cortex-M3 targets using just the NVIC without
+ * requiring SRST, getting a SoC reset (or a core-only reset)
+ * instead of a system reset.
+ */
+ if (!(jtag_reset_config & RESET_HAS_SRST))
+ assert_srst = 0;
+
+ /* Enable debug requests */
+ mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
+ mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+
+ mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
+
+ if (!target->reset_halt)
+ {
+ /* Set/Clear C_MASKINTS in a separate operation */
+ if (cortex_m3->dcb_dhcsr & C_MASKINTS)
+ mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT);
+
+ /* clear any debug flags before resuming */
+ cortex_m3_clear_halt(target);
+
+ /* clear C_HALT in dhcsr reg */
+ cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
+
+ /* Enter debug state on reset, cf. end_reset_event() */
+ mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
+ }
+ else
+ {
+ /* Enter debug state on reset, cf. end_reset_event() */
+ mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
+ }
+
+ /*
+ * When nRST is asserted on most Stellaris devices, it clears some of
+ * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
+ * and OpenOCD depends on those TRMs. So we won't use SRST on those
+ * chips. (Only power-on reset should affect debug state, beyond a
+ * few specified bits; not the chip's nRST input, wired to SRST.)
+ *
+ * REVISIT current errata specs don't seem to cover this issue.
+ * Do we have more details than this email?
+ * https://lists.berlios.de/pipermail
+ * /openocd-development/2008-August/003065.html
+ */
+ if (strcmp(target->variant, "lm3s") == 0)
+ {
+ /* Check for silicon revisions with the issue. */
+ uint32_t did0;
+
+ if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)