mips: fixup fastdata

[openocd.git] / src / target / cortex_m3.c

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index f2947ad118be189bc68ebb3aea2b14e4da2e29b4..269d2a67ffeebc7104ff442c5302e88dc58fd9a7 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -927,14 +927,14 @@ static int cortex_m3_assert_reset(struct target *target)
 
        enum reset_types jtag_reset_config = jtag_get_reset_config();
 
-       /*
-        * We can reset Cortex-M3 targets using just the NVIC without
-        * requiring SRST, getting a SoC reset (or a core-only reset)
-        * instead of a system reset.
-        */
-       if (!(jtag_reset_config & RESET_HAS_SRST) &&
-                       (cortex_m3->soft_reset_config == CORTEX_M3_RESET_SRST)) {
-               reset_config = CORTEX_M3_RESET_VECTRESET;
+       if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
+               /* allow scripts to override the reset event */
+
+               target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
+               register_cache_invalidate(cortex_m3->armv7m.core_cache);
+               target->state = TARGET_RESET;
+
+               return ERROR_OK;
        }
 
        /* Enable debug requests */
@@ -984,7 +984,7 @@ static int cortex_m3_assert_reset(struct target *target)
                        return retval;
        }
 
-       if (reset_config == CORTEX_M3_RESET_SRST)
+       if (jtag_reset_config & RESET_HAS_SRST)
        {
                /* default to asserting srst */
                if (jtag_reset_config & RESET_SRST_PULLS_TRST)
@@ -1543,7 +1543,7 @@ static int cortex_m3_store_core_reg_u32(struct target *target,
                {
                        struct reg *r;
 
-                       LOG_ERROR("JTAG failure %i", retval);
+                       LOG_ERROR("JTAG failure");
                        r = armv7m->core_cache->reg_list + num;
                        r->dirty = r->valid;
                        return ERROR_JTAG_DEVICE_ERROR;
@@ -1618,7 +1618,7 @@ static int cortex_m3_read_memory(struct target *target, uint32_t address,
 }
 
 static int cortex_m3_write_memory(struct target *target, uint32_t address,
-               uint32_t size, uint32_t count, uint8_t *buffer)
+               uint32_t size, uint32_t count, const uint8_t *buffer)
 {
        struct armv7m_common *armv7m = target_to_armv7m(target);
        struct adiv5_dap *swjdp = &armv7m->dap;
@@ -1642,7 +1642,7 @@ static int cortex_m3_write_memory(struct target *target, uint32_t address,
 }
 
 static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
-               uint32_t count, uint8_t *buffer)
+               uint32_t count, const uint8_t *buffer)
 {
        return cortex_m3_write_memory(target, address, 4, count, buffer);
 }
@@ -1945,7 +1945,7 @@ static int cortex_m3_init_arch_info(struct target *target,
 
        /* default reset mode is to use srst if fitted
         * if not it will use CORTEX_M3_RESET_VECTRESET */
-       cortex_m3->soft_reset_config = CORTEX_M3_RESET_SRST;
+       cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
 
        armv7m->arm.dap = &armv7m->dap;
 
@@ -2138,16 +2138,10 @@ COMMAND_HANDLER(handle_cortex_m3_reset_config_command)
                        cortex_m3->soft_reset_config = CORTEX_M3_RESET_SYSRESETREQ;
                else if (strcmp(*CMD_ARGV, "vectreset") == 0)
                        cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
-               else
-                       cortex_m3->soft_reset_config = CORTEX_M3_RESET_SRST;
        }
 
        switch (cortex_m3->soft_reset_config)
        {
-               case CORTEX_M3_RESET_SRST:
-                       reset_config = "srst";
-                       break;
-
                case CORTEX_M3_RESET_SYSRESETREQ:
                        reset_config = "sysresetreq";
                        break;