#define FP_COMP6 0xE0002020
#define FP_COMP7 0xE0002024
+#define FPU_CPACR 0xE000ED88
+#define FPU_FPCCR 0xE000EF34
+#define FPU_FPCAR 0xE000EF38
+#define FPU_FPDSCR 0xE000EF3C
+
/* DCB_DHCSR bit and field definitions */
#define DBGKEY (0xA05F << 16)
#define C_DEBUGEN (1 << 0)
#define S_RESET_ST (1 << 25)
/* DCB_DEMCR bit and field definitions */
-#define TRCENA (1 << 24)
-#define VC_HARDERR (1 << 10)
-#define VC_INTERR (1 << 9)
-#define VC_BUSERR (1 << 8)
-#define VC_STATERR (1 << 7)
-#define VC_CHKERR (1 << 6)
-#define VC_NOCPERR (1 << 5)
-#define VC_MMERR (1 << 4)
-#define VC_CORERESET (1 << 0)
+#define TRCENA (1 << 24)
+#define VC_HARDERR (1 << 10)
+#define VC_INTERR (1 << 9)
+#define VC_BUSERR (1 << 8)
+#define VC_STATERR (1 << 7)
+#define VC_CHKERR (1 << 6)
+#define VC_NOCPERR (1 << 5)
+#define VC_MMERR (1 << 4)
+#define VC_CORERESET (1 << 0)
#define NVIC_ICTR 0xE000E004
#define NVIC_ISE0 0xE000E100
struct cortex_m3_common, armv7m);
}
+int cortex_m3_examine(struct target *target);
int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
int cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
int cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint);
int cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
int cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
+void cortex_m3_enable_breakpoints(struct target *target);
void cortex_m3_enable_watchpoints(struct target *target);
void cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target);