cortex_m: fix reading of DCB_DSCSR register

[openocd.git] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 8e55014f9b022c3c208b613f31b3e30c08dfcc03..ebc3bac999fd56de77d7c0b2ee826e2ab9630409 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -801,15 +801,11 @@ static int cortex_m_debug_entry(struct target *target)
                return retval;
 
        /* examine PE security state */
-       bool secure_state = false;
+       uint32_t dscsr = 0;
        if (armv7m->arm.arch == ARM_ARCH_V8M) {
-               uint32_t dscsr;
-
                retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr);
                if (retval != ERROR_OK)
                        return retval;
-
-               secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
        }
 
        /* Load all registers to arm.core_cache */
@@ -857,6 +853,7 @@ static int cortex_m_debug_entry(struct target *target)
        if (armv7m->exception_number)
                cortex_m_examine_exception_reason(target);
 
+       bool secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
        LOG_TARGET_DEBUG(target, "entered debug state in core mode: %s at PC 0x%" PRIx32
                        ", cpu in %s state, target->state: %s",
                arm_mode_name(arm->core_mode),