armv7m: use generic arm::core_mode

[openocd.git] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 4d9daf5ca09e48de924fda94476f4b207655107d..89d70beceb7769b604825bf39399c84fdc3c877c 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -451,18 +451,16 @@ static int cortex_m3_debug_entry(struct target *target)
 
        /* Are we in an exception handler */
        if (xPSR & 0x1FF) {
-               armv7m->core_mode = ARMV7M_MODE_HANDLER;
                armv7m->exception_number = (xPSR & 0x1FF);
 
                arm->core_mode = ARM_MODE_HANDLER;
                arm->map = armv7m_msp_reg_map;
        } else {
-               unsigned control = buf_get_u32(armv7m->core_cache
+               unsigned control = buf_get_u32(arm->core_cache
                                ->reg_list[ARMV7M_CONTROL].value, 0, 2);
 
                /* is this thread privileged? */
-               armv7m->core_mode = control & 1;
-               arm->core_mode = armv7m->core_mode
+               arm->core_mode = control & 1
                        ? ARM_MODE_USER_THREAD
                        : ARM_MODE_THREAD;
 
@@ -479,7 +477,7 @@ static int cortex_m3_debug_entry(struct target *target)
                cortex_m3_examine_exception_reason(target);
 
        LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
-               armv7m_mode_strings[armv7m->core_mode],
+               arm_mode_name(arm->core_mode),
                *(uint32_t *)(arm->pc->value),
                target_state_name(target));
 
@@ -677,7 +675,7 @@ static int cortex_m3_soft_reset_halt(struct target *target)
        return ERROR_OK;
 }
 
-static void cortex_m3_enable_breakpoints(struct target *target)
+void cortex_m3_enable_breakpoints(struct target *target)
 {
        struct breakpoint *breakpoint = target->breakpoints;