{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = &armv7a->dap;
-
int retval;
uint32_t dummy;
/* Unlocking the debug registers for modification */
/* The debugport might be uninitialised so try twice */
- retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
+ retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
+ armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
if (retval != ERROR_OK)
{
/* try again */
- retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
+ retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
+ armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
if (retval == ERROR_OK)
{
LOG_USER("Locking debug access failed on first, but succeeded on second try.");
return retval;
/* Clear Sticky Power Down status Bit in PRSR to enable access to
the registers in the Core Power Domain */
- retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
+ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
+ armv7a->debug_base + CPUDBG_PRSR, &dummy);
if (retval != ERROR_OK)
return retval;
/* Resync breakpoint registers */
/* Since this is likely called from init or reset, update target state information*/
- retval = cortex_a9_poll(target);
-
- return retval;
+ return cortex_a9_poll(target);
}
/* To reduce needless round-trips, pass in a pointer to the current
long long then = timeval_ms();
while ((dscr & DSCR_INSTR_COMP) == 0)
{
- retval = mem_ap_read_atomic_u32(swjdp,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
{
}
}
- retval = mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
+ retval = mem_ap_sel_write_u32(swjdp, swjdp_debugap,
+ armv7a->debug_base + CPUDBG_ITR, opcode);
if (retval != ERROR_OK)
return retval;
then = timeval_ms();
do
{
- retval = mem_ap_read_atomic_u32(swjdp,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK)
return retval;
- dap_ap_select(swjdp, swjdp_memoryap);
- retval = mem_ap_read_buf_u32(swjdp, (uint8_t *)(®file[1]), 4*15, address);
- if (retval != ERROR_OK)
- return retval;
- dap_ap_select(swjdp, swjdp_debugap);
+ retval = mem_ap_sel_read_buf_u32(swjdp, swjdp_memoryap,
+ (uint8_t *)(®file[1]), 4*15, address);
return retval;
}
long long then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) == 0)
{
- retval = mem_ap_read_atomic_u32(swjdp,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
}
}
- retval = mem_ap_read_atomic_u32(swjdp,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_DTRTX, value);
LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
/* Check that DCCRX is not full */
- retval = mem_ap_read_atomic_u32(swjdp,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
if (dscr & DSCR_DTR_RX_FULL)
{
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
- /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
+ /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */
retval = cortex_a9_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
/* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
LOG_DEBUG("write DCC 0x%08" PRIx32, value);
- retval = mem_ap_write_u32(swjdp,
+ retval = mem_ap_sel_write_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_DTRRX, value);
if (retval != ERROR_OK)
return retval;
if (Rd < 15)
{
- /* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */
+ /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
retval = cortex_a9_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
&dscr);
if (retval != ERROR_OK)
}
else if (Rd == 15)
{
- /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
+ /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
* then "mov r15, r0"
*/
retval = cortex_a9_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
}
else
{
- /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
+ /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
* then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
*/
retval = cortex_a9_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = &armv7a->dap;
- retval = mem_ap_write_atomic_u32(swjdp, address, value);
+ retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, address, value);
return retval;
}
static int cortex_a9_write_dcc(struct cortex_a9_common *a9, uint32_t data)
{
LOG_DEBUG("write DCC 0x%08" PRIx32, data);
- return mem_ap_write_u32(&a9->armv7a_common.dap,
+ return mem_ap_sel_write_u32(&a9->armv7a_common.dap, swjdp_debugap,
a9->armv7a_common.debug_base + CPUDBG_DTRRX, data);
}
/* Wait for DTRRXfull */
long long then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) == 0) {
- retval = mem_ap_read_atomic_u32(swjdp,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
a9->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
if (retval != ERROR_OK)
}
}
- retval = mem_ap_read_atomic_u32(swjdp,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
a9->armv7a_common.debug_base + CPUDBG_DTRTX, data);
if (retval != ERROR_OK)
return retval;
long long then = timeval_ms();
for (;;)
{
- retval = mem_ap_read_atomic_u32(swjdp,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
a9->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
if (retval != ERROR_OK)
struct armv7a_common *armv7a = &cortex_a9->armv7a_common;
struct adiv5_dap *swjdp = &armv7a->dap;
enum target_state prev_target_state = target->state;
- uint8_t saved_apsel = dap_ap_get_select(swjdp);
- dap_ap_select(swjdp, swjdp_debugap);
- retval = mem_ap_read_atomic_u32(swjdp,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
{
- dap_ap_select(swjdp, saved_apsel);
return retval;
}
cortex_a9->cpudbg_dscr = dscr;
target->state = TARGET_UNKNOWN;
}
- dap_ap_select(swjdp, saved_apsel);
-
return retval;
}
uint32_t dscr;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = &armv7a->dap;
- uint8_t saved_apsel = dap_ap_get_select(swjdp);
- dap_ap_select(swjdp, swjdp_debugap);
/*
* Tell the core to be halted by writing DRCR with 0x1
* and then wait for the core to be halted.
*/
- retval = mem_ap_write_atomic_u32(swjdp,
+ retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_HALT);
if (retval != ERROR_OK)
- goto out;
+ return retval;
/*
* enter halting debug mode
*/
- retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
- goto out;
+ return retval;
- retval = mem_ap_write_atomic_u32(swjdp,
+ retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
if (retval != ERROR_OK)
- goto out;
+ return retval;
long long then = timeval_ms();
for (;;)
{
- retval = mem_ap_read_atomic_u32(swjdp,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
- goto out;
+ return retval;
if ((dscr & DSCR_CORE_HALTED) != 0)
{
break;
target->debug_reason = DBG_REASON_DBGRQ;
-out:
- dap_ap_select(swjdp, saved_apsel);
- return retval;
+ return ERROR_OK;
}
static int cortex_a9_resume(struct target *target, int current,
// struct breakpoint *breakpoint = NULL;
uint32_t resume_pc, dscr;
- uint8_t saved_apsel = dap_ap_get_select(swjdp);
- dap_ap_select(swjdp, swjdp_debugap);
-
if (!debug_execution)
target_free_all_working_areas(target);
* disable IRQs by default, with optional override...
*/
- retval = mem_ap_read_atomic_u32(swjdp,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
if ((dscr & DSCR_INSTR_COMP) == 0)
LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
- retval = mem_ap_write_atomic_u32(swjdp,
+ retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN);
if (retval != ERROR_OK)
return retval;
- retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR,
- DRCR_RESTART | DRCR_CLEAR_EXCEPTIONS);
+ retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
+ armv7a->debug_base + CPUDBG_DRCR, DRCR_RESTART | DRCR_CLEAR_EXCEPTIONS);
if (retval != ERROR_OK)
return retval;
long long then = timeval_ms();
for (;;)
{
- retval = mem_ap_read_atomic_u32(swjdp,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc);
}
- dap_ap_select(swjdp, saved_apsel);
-
return ERROR_OK;
}
LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a9->cpudbg_dscr);
/* REVISIT surely we should not re-read DSCR !! */
- retval = mem_ap_read_atomic_u32(swjdp,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
/* Enable the ITR execution once we are in debug mode */
dscr |= DSCR_ITR_EN;
- retval = mem_ap_write_atomic_u32(swjdp,
+ retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_DSCR, dscr);
if (retval != ERROR_OK)
return retval;
if (target->debug_reason == DBG_REASON_WATCHPOINT) {
uint32_t wfar;
- retval = mem_ap_read_atomic_u32(swjdp,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_WFAR,
&wfar);
if (retval != ERROR_OK)
}
else
{
- dap_ap_select(swjdp, swjdp_memoryap);
retval = cortex_a9_read_regs_through_mem(target,
regfile_working_area->address, regfile);
- dap_ap_select(swjdp, swjdp_memoryap);
+
target_free_working_area(target, regfile_working_area);
if (retval != ERROR_OK)
{
retval = cortex_a9_dap_read_coreregister_u32(target, &cpsr, 16);
if (retval != ERROR_OK)
return retval;
- dap_ap_select(swjdp, swjdp_debugap);
+
LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
arm_set_cpsr(armv4_5, cpsr);
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = &armv7a->dap;
int retval = ERROR_INVALID_ARGUMENTS;
- uint8_t saved_apsel = dap_ap_get_select(swjdp);
-
- /* cortex_a9 handles unaligned memory access */
-
- dap_ap_select(swjdp, swjdp_memoryap);
+ uint8_t apsel = dap_ap_get_select(swjdp);
LOG_DEBUG("Reading memory at real address 0x%x; size %d; count %d", address, size, count);
+
if (count && buffer) {
- switch (size) {
- case 4:
- retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
- break;
- case 2:
- retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
- break;
- case 1:
- retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
- break;
+
+ if ( apsel == swjdp_memoryap ) {
+
+ /* read memory through AHB-AP */
+
+ switch (size) {
+ case 4:
+ retval = mem_ap_sel_read_buf_u32(swjdp, swjdp_memoryap,
+ buffer, 4 * count, address);
+ break;
+ case 2:
+ retval = mem_ap_sel_read_buf_u16(swjdp, swjdp_memoryap,
+ buffer, 2 * count, address);
+ break;
+ case 1:
+ retval = mem_ap_sel_read_buf_u8(swjdp, swjdp_memoryap,
+ buffer, count, address);
+ break;
+ }
+
+ } else {
+
+ /* read memory through APB-AP */
+
+ uint32_t saved_r0, saved_r1;
+ int nbytes = count * size;
+ uint32_t data;
+ int enabled = 0;
+
+ if (target->state != TARGET_HALTED)
+ {
+ LOG_WARNING("target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ retval = cortex_a9_mmu(target, &enabled);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (enabled)
+ {
+ LOG_WARNING("Reading physical memory through APB with MMU enabled is not yet implemented");
+ return ERROR_TARGET_FAILURE;
+ }
+
+ /* save registers r0 and r1, we are going to corrupt them */
+ retval = cortex_a9_dap_read_coreregister_u32(target, &saved_r0, 0);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = cortex_a9_dap_read_coreregister_u32(target, &saved_r1, 1);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = cortex_a9_dap_write_coreregister_u32(target, address, 0);
+ if (retval != ERROR_OK)
+ return retval;
+
+ while (nbytes > 0) {
+
+ /* execute instruction LDRB r1, [r0], 1 (0xe4d01001) */
+ retval = cortex_a9_exec_opcode(target, ARMV4_5_LDRB_IP(1, 0) , NULL);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = cortex_a9_dap_read_coreregister_u32(target, &data, 1);
+ if (retval != ERROR_OK)
+ return retval;
+
+ *buffer++ = data;
+ --nbytes;
+
+ }
+
+ /* restore corrupted registers r0 and r1 */
+ retval = cortex_a9_dap_write_coreregister_u32(target, saved_r0, 0);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = cortex_a9_dap_write_coreregister_u32(target, saved_r1, 1);
+ if (retval != ERROR_OK)
+ return retval;
+
}
}
- dap_ap_select(swjdp, saved_apsel);
-
return retval;
}
LOG_DEBUG("Writing memory to real address 0x%x; size %d; count %d", address, size, count);
if (count && buffer) {
- uint8_t saved_apsel = dap_ap_get_select(swjdp);
- dap_ap_select(swjdp, swjdp_memoryap);
-
- switch (size) {
- case 4:
- retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
- break;
- case 2:
- retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
- break;
- case 1:
- retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
- break;
- }
+ uint8_t apsel = dap_ap_get_select(swjdp);
+
+ if ( apsel == swjdp_memoryap ) {
+
+ /* write memory through AHB-AP */
+ switch (size) {
+ case 4:
+ retval = mem_ap_sel_write_buf_u32(swjdp, swjdp_memoryap,
+ buffer, 4 * count, address);
+ break;
+ case 2:
+ retval = mem_ap_sel_write_buf_u16(swjdp, swjdp_memoryap,
+ buffer, 2 * count, address);
+ break;
+ case 1:
+ retval = mem_ap_sel_write_buf_u8(swjdp, swjdp_memoryap,
+ buffer, count, address);
+ break;
+ }
+
+ } else {
- dap_ap_select(swjdp, saved_apsel);
+ /* write memory through APB-AP */
+
+ uint32_t saved_r0, saved_r1;
+ int nbytes = count * size;
+ uint32_t data;
+ int enabled = 0;
+
+ if (target->state != TARGET_HALTED)
+ {
+ LOG_WARNING("target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ retval = cortex_a9_mmu(target, &enabled);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (enabled)
+ {
+ LOG_WARNING("Writing physical memory through APB with MMU enabled is not yet implemented");
+ return ERROR_TARGET_FAILURE;
+ }
+
+ /* save registers r0 and r1, we are going to corrupt them */
+ retval = cortex_a9_dap_read_coreregister_u32(target, &saved_r0, 0);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = cortex_a9_dap_read_coreregister_u32(target, &saved_r1, 1);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = cortex_a9_dap_write_coreregister_u32(target, address, 0);
+ if (retval != ERROR_OK)
+ return retval;
+
+ while (nbytes > 0) {
+
+ data = *buffer++;
+
+ retval = cortex_a9_dap_write_coreregister_u32(target, data, 1);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* execute instruction STRB r1, [r0], 1 (0xe4c01001) */
+ retval = cortex_a9_exec_opcode(target, ARMV4_5_STRB_IP(1, 0) , NULL);
+ if (retval != ERROR_OK)
+ return retval;
+
+ --nbytes;
+ }
+
+ /* restore corrupted registers r0 and r1 */
+ retval = cortex_a9_dap_write_coreregister_u32(target, saved_r0, 0);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = cortex_a9_dap_write_coreregister_u32(target, saved_r1, 1);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* we can return here without invalidating D/I-cache because */
+ /* access through APB maintains cache coherency */
+ return retval;
+ }
}
if (retval != ERROR_OK)
return retval;
- dap_ap_select(swjdp, swjdp_debugap);
-
/*
* FIXME: assuming omap4430
*
armv7a->debug_base = 0x80000000 |
((target->coreid & 0x3) << CORTEX_A9_PADDRDBG_CPU_SHIFT);
- retval = mem_ap_read_atomic_u32(swjdp,
+ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_CPUID, &cpuid);
if (retval != ERROR_OK)
return retval;
- if ((retval = mem_ap_read_atomic_u32(swjdp,
+ if ((retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
{
LOG_DEBUG("Examine %s failed", "CPUID");
return retval;
}
- if ((retval = mem_ap_read_atomic_u32(swjdp,
+ if ((retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
{
LOG_DEBUG("Examine %s failed", "CTYPR");
return retval;
}
- if ((retval = mem_ap_read_atomic_u32(swjdp,
+ if ((retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
{
LOG_DEBUG("Examine %s failed", "TTYPR");
return retval;
}
- if ((retval = mem_ap_read_atomic_u32(swjdp,
+ if ((retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK)
{
LOG_DEBUG("Examine %s failed", "DIDR");
Code Review / openocd.git / blobdiff