int retval = ERROR_OK;
uint32_t didr, ctypr, ttypr, cpuid;
- LOG_DEBUG("TODO");
+ /* stop assuming this is an OMAP! */
+ LOG_DEBUG("TODO - autoconfigure");
/* Here we shall insert a proper ROM Table scan */
armv7a->debug_base = OMAP3530_DEBUG_BASE;
if ((retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
{
- LOG_DEBUG("Examine failed");
+ LOG_DEBUG("Examine %s failed", "CPUID");
return retval;
}
if ((retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
{
- LOG_DEBUG("Examine failed");
+ LOG_DEBUG("Examine %s failed", "CTYPR");
return retval;
}
if ((retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
{
- LOG_DEBUG("Examine failed");
+ LOG_DEBUG("Examine %s failed", "TTYPR");
return retval;
}
if ((retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK)
{
- LOG_DEBUG("Examine failed");
+ LOG_DEBUG("Examine %s failed", "DIDR");
return retval;
}
static const struct command_registration cortex_a8_exec_command_handlers[] = {
{
.name = "cache_info",
- .handler = &cortex_a8_handle_cache_info_command,
+ .handler = cortex_a8_handle_cache_info_command,
.mode = COMMAND_EXEC,
.help = "display information about target caches",
},
{
.name = "dbginit",
- .handler = &cortex_a8_handle_dbginit_command,
+ .handler = cortex_a8_handle_dbginit_command,
.mode = COMMAND_EXEC,
.help = "Initialize core debug",
},