ARM semihosting: win32 and cygwin fixes

[openocd.git] / src / target / cortex_a8.c

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 14cbb9d77b453614020b99b01d9019a869f94774..bcdb526017dc3063972d82c2b4747a7bc5b4de4f 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -38,6 +38,7 @@
 #include "register.h"
 #include "target_request.h"
 #include "target_type.h"
+#include "arm_opcodes.h"
 
 static int cortex_a8_poll(struct target *target);
 static int cortex_a8_debug_entry(struct target *target);
@@ -705,17 +706,17 @@ static int cortex_a8_resume(struct target *target, int current,
         */
        switch (armv4_5->core_state)
        {
-       case ARMV4_5_STATE_ARM:
+       case ARM_STATE_ARM:
                resume_pc &= 0xFFFFFFFC;
                break;
-       case ARMV4_5_STATE_THUMB:
+       case ARM_STATE_THUMB:
        case ARM_STATE_THUMB_EE:
                /* When the return address is loaded into PC
                 * bit 0 must be 1 to stay in Thumb state
                 */
                resume_pc |= 0x1;
                break;
-       case ARMV4_5_STATE_JAZELLE:
+       case ARM_STATE_JAZELLE:
                LOG_ERROR("How do I resume into Jazelle state??");
                return ERROR_FAIL;
        }
@@ -782,7 +783,7 @@ static int cortex_a8_resume(struct target *target, int current,
 static int cortex_a8_debug_entry(struct target *target)
 {
        int i;
-       uint32_t regfile[16], wfar, cpsr, dscr;
+       uint32_t regfile[16], cpsr, dscr;
        int retval = ERROR_OK;
        struct working_area *regfile_working_area = NULL;
        struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
@@ -793,6 +794,7 @@ static int cortex_a8_debug_entry(struct target *target)
 
        LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
 
+       /* REVISIT surely we should not re-read DSCR !! */
        mem_ap_read_atomic_u32(swjdp,
                                armv7a->debug_base + CPUDBG_DSCR, &dscr);
 
@@ -807,30 +809,16 @@ static int cortex_a8_debug_entry(struct target *target)
                        armv7a->debug_base + CPUDBG_DSCR, dscr);
 
        /* Examine debug reason */
-       switch (DSCR_ENTRY(cortex_a8->cpudbg_dscr))
-       {
-               case 0:         /* DRCR[0] write */
-               case 4:         /* EDBGRQ */
-                       target->debug_reason = DBG_REASON_DBGRQ;
-                       break;
-               case 1:         /* HW breakpoint */
-               case 3:         /* SW BKPT */
-               case 5:         /* vector catch */
-                       target->debug_reason = DBG_REASON_BREAKPOINT;
-                       break;
-               case 2:         /* asynch watchpoint */
-               case 10:        /* precise watchpoint */
-                       target->debug_reason = DBG_REASON_WATCHPOINT;
-
-                       /* save address of faulting instruction */
-                       retval = mem_ap_read_atomic_u32(swjdp,
-                                       armv7a->debug_base + CPUDBG_WFAR,
-                                       &wfar);
-                       arm_dpm_report_wfar(&armv7a->dpm, wfar);
-                       break;
-               default:
-                       target->debug_reason = DBG_REASON_UNDEFINED;
-                       break;
+       arm_dpm_report_dscr(&armv7a->dpm, cortex_a8->cpudbg_dscr);
+
+       /* save address of instruction that triggered the watchpoint? */
+       if (target->debug_reason == DBG_REASON_WATCHPOINT) {
+               uint32_t wfar;
+
+               retval = mem_ap_read_atomic_u32(swjdp,
+                               armv7a->debug_base + CPUDBG_WFAR,
+                               &wfar);
+               arm_dpm_report_wfar(&armv7a->dpm, wfar);
        }
 
        /* REVISIT fast_reg_read is never set ... */
@@ -987,7 +975,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 
        /* Setup single step breakpoint */
        stepbreakpoint.address = address;
-       stepbreakpoint.length = (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+       stepbreakpoint.length = (armv4_5->core_state == ARM_STATE_THUMB)
                        ? 2 : 4;
        stepbreakpoint.type = BKPT_HARD;
        stepbreakpoint.set = 0;
@@ -1473,7 +1461,8 @@ static int cortex_a8_examine_first(struct target *target)
        int retval = ERROR_OK;
        uint32_t didr, ctypr, ttypr, cpuid;
 
-       LOG_DEBUG("TODO");
+       /* stop assuming this is an OMAP! */
+       LOG_DEBUG("TODO - autoconfigure");
 
        /* Here we shall insert a proper ROM Table scan */
        armv7a->debug_base = OMAP3530_DEBUG_BASE;
@@ -1486,28 +1475,28 @@ static int cortex_a8_examine_first(struct target *target)
        if ((retval = mem_ap_read_atomic_u32(swjdp,
                        armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
        {
-               LOG_DEBUG("Examine failed");
+               LOG_DEBUG("Examine %s failed", "CPUID");
                return retval;
        }
 
        if ((retval = mem_ap_read_atomic_u32(swjdp,
                        armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
        {
-               LOG_DEBUG("Examine failed");
+               LOG_DEBUG("Examine %s failed", "CTYPR");
                return retval;
        }
 
        if ((retval = mem_ap_read_atomic_u32(swjdp,
                        armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
        {
-               LOG_DEBUG("Examine failed");
+               LOG_DEBUG("Examine %s failed", "TTYPR");
                return retval;
        }
 
        if ((retval = mem_ap_read_atomic_u32(swjdp,
                        armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK)
        {
-               LOG_DEBUG("Examine failed");
+               LOG_DEBUG("Examine %s failed", "DIDR");
                return retval;
        }
 
@@ -1615,7 +1604,7 @@ static int cortex_a8_init_arch_info(struct target *target,
 //     arm7_9->handle_target_request = cortex_a8_handle_target_request;
 
        /* REVISIT v7a setup should be in a v7a-specific routine */
-       armv4_5_init_arch_info(target, armv4_5);
+       arm_init_arch_info(target, armv4_5);
        armv7a->common_magic = ARMV7_COMMON_MAGIC;
 
        target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
@@ -1654,13 +1643,13 @@ COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
 static const struct command_registration cortex_a8_exec_command_handlers[] = {
        {
                .name = "cache_info",
-               .handler = &cortex_a8_handle_cache_info_command,
+               .handler = cortex_a8_handle_cache_info_command,
                .mode = COMMAND_EXEC,
                .help = "display information about target caches",
        },
        {
                .name = "dbginit",
-               .handler = &cortex_a8_handle_dbginit_command,
+               .handler = cortex_a8_handle_dbginit_command,
                .mode = COMMAND_EXEC,
                .help = "Initialize core debug",
        },
@@ -1698,7 +1687,8 @@ struct target_type cortexa8_target = {
        .deassert_reset = cortex_a8_deassert_reset,
        .soft_reset_halt = NULL,
 
-       .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+       /* REVISIT allow exporting VFP3 registers ... */
+       .get_gdb_reg_list = arm_get_gdb_reg_list,
 
        .read_memory = cortex_a8_read_memory,
        .write_memory = cortex_a8_write_memory,