ARM11: use standard single step simulation

[openocd.git] / src / target / cortex_a8.c

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index de579feb724ddbec71a3550235a1f5d2213f405b..b006e81a64df7f91547fce2a4020b70d2042c083 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -496,8 +496,7 @@ static int cortex_a8_resume(struct target *target, int current,
 
        /* current = 1: continue on current pc, otherwise continue at <address> */
        resume_pc = buf_get_u32(
-                       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-                               armv4_5->core_mode, 15).value,
+                       armv4_5->core_cache->reg_list[15].value,
                        0, 32);
        if (!current)
                resume_pc = address;
@@ -522,13 +521,10 @@ static int cortex_a8_resume(struct target *target, int current,
                return ERROR_FAIL;
        }
        LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
-       buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-                               armv4_5->core_mode, 15).value,
+       buf_set_u32(armv4_5->core_cache->reg_list[15].value,
                        0, 32, resume_pc);
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-                       armv4_5->core_mode, 15).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-                       armv4_5->core_mode, 15).valid = 1;
+       armv4_5->core_cache->reg_list[15].dirty = 1;
+       armv4_5->core_cache->reg_list[15].valid = 1;
 
        cortex_a8_restore_context(target);
 
@@ -653,8 +649,7 @@ static int cortex_a8_debug_entry(struct target *target)
        /* update cache */
        for (i = 0; i <= ARM_PC; i++)
        {
-               reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-                                       armv4_5->core_mode, i);
+               reg = arm_reg_current(armv4_5, i);
 
                buf_set_u32(reg->value, 0, 32, regfile[i]);
                reg->valid = 1;
@@ -672,13 +667,10 @@ static int cortex_a8_debug_entry(struct target *target)
                // ARM state
                regfile[ARM_PC] -= 8;
        }
-       buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-                               armv4_5->core_mode, ARM_PC).value,
-                       0, 32, regfile[ARM_PC]);
 
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
-               .dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-                               armv4_5->core_mode, 0).valid;
+       reg = armv4_5->core_cache->reg_list + 15;
+       buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
+       reg->dirty = reg->valid;
        ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
                .dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 15).valid;