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cortex a8: mem_ap_read_buf_u32() error handling
[openocd.git] / src / target / cortex_a8.c
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 1577c26841681ea080ff6a50512ffef221571876..a2f3ea060bb710143fd915d69acd2044fa27b075 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -11,6 +11,9 @@
  *   Copyright (C) 2009 by Dirk Behme                                      *
  *   dirk.behme@gmail.com - copy from cortex_m3                            *
  *                                                                         *
+ *   Copyright (C) 2010 Øyvind Harboe                                      *
+ *   oyvind.harboe@zylin.com                                               *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -39,6 +42,7 @@
 #include "target_request.h"
 #include "target_type.h"
 #include "arm_opcodes.h"
+#include <helper/time_support.h>
 
 static int cortex_a8_poll(struct target *target);
 static int cortex_a8_debug_entry(struct target *target);
@@ -91,18 +95,25 @@ static int cortex_a8_init_debug_access(struct target *target)
        {
                /* try again */
                retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
+               if (retval == ERROR_OK)
+               {
+                       LOG_USER("Locking debug access failed on first, but succeeded on second try.");
+               }
        }
        if (retval != ERROR_OK)
                return retval;
        /* Clear Sticky Power Down status Bit in PRSR to enable access to
           the registers in the Core Power Domain */
        retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
+       if (retval != ERROR_OK)
+               return retval;
+
        /* Enabling of instruction execution in debug mode is done in debug_entry code */
 
        /* Resync breakpoint registers */
 
-       /* Since this is likley called from init or reset, update targtet state information*/
-       cortex_a8_poll(target);
+       /* Since this is likely called from init or reset, update target state information*/
+       retval = cortex_a8_poll(target);
 
        return retval;
 }
@@ -136,7 +147,9 @@ static int cortex_a8_exec_opcode(struct target *target,
                }
        }
 
-       mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
+       retval = mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
+       if (retval != ERROR_OK)
+               return retval;
 
        do
        {
@@ -167,11 +180,20 @@ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t addre
        struct armv7a_common *armv7a = target_to_armv7a(target);
        struct adiv5_dap *swjdp = &armv7a->dap;
 
-       cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
-       cortex_a8_dap_write_coreregister_u32(target, address, 0);
-       cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
+       retval = cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = cortex_a8_dap_write_coreregister_u32(target, address, 0);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
+       if (retval != ERROR_OK)
+               return retval;
+
        dap_ap_select(swjdp, swjdp_memoryap);
-       mem_ap_read_buf_u32(swjdp, (uint8_t *)(&regfile[1]), 4*15, address);
+       retval = mem_ap_read_buf_u32(swjdp, (uint8_t *)(&regfile[1]), 4*15, address);
+       if (retval != ERROR_OK)
+               return retval;
        dap_ap_select(swjdp, swjdp_debugap);
 
        return retval;
@@ -192,27 +214,37 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
        if (reg < 15)
        {
                /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0"  0xEE00nE15 */
-               cortex_a8_exec_opcode(target,
+               retval = cortex_a8_exec_opcode(target,
                                ARMV4_5_MCR(14, 0, reg, 0, 5, 0),
                                &dscr);
+               if (retval != ERROR_OK)
+                       return retval;
        }
        else if (reg == 15)
        {
                /* "MOV r0, r15"; then move r0 to DCCTX */
-               cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr);
-               cortex_a8_exec_opcode(target,
+               retval = cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr);
+               if (retval != ERROR_OK)
+                       return retval;
+               retval = cortex_a8_exec_opcode(target,
                                ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
                                &dscr);
+               if (retval != ERROR_OK)
+                       return retval;
        }
        else
        {
                /* "MRS r0, CPSR" or "MRS r0, SPSR"
                 * then move r0 to DCCTX
                 */
-               cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
-               cortex_a8_exec_opcode(target,
+               retval = cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
+               if (retval != ERROR_OK)
+                       return retval;
+               retval = cortex_a8_exec_opcode(target,
                                ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
                                &dscr);
+               if (retval != ERROR_OK)
+                       return retval;
        }
 
        /* Wait for DTRRXfull then read DTRRTX */
@@ -220,6 +252,8 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
        {
                retval = mem_ap_read_atomic_u32(swjdp,
                                armv7a->debug_base + CPUDBG_DSCR, &dscr);
+               if (retval != ERROR_OK)
+                       return retval;
        }
 
        retval = mem_ap_read_atomic_u32(swjdp,
@@ -243,12 +277,16 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
        /* Check that DCCRX is not full */
        retval = mem_ap_read_atomic_u32(swjdp,
                                armv7a->debug_base + CPUDBG_DSCR, &dscr);
+       if (retval != ERROR_OK)
+               return retval;
        if (dscr & DSCR_DTR_RX_FULL)
        {
                LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
                /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode  0xEE000E15 */
-               cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+               retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
                                &dscr);
+               if (retval != ERROR_OK)
+                       return retval;
        }
 
        if (Rd > 17)
@@ -258,37 +296,53 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
        LOG_DEBUG("write DCC 0x%08" PRIx32, value);
        retval = mem_ap_write_u32(swjdp,
                        armv7a->debug_base + CPUDBG_DTRRX, value);
+       if (retval != ERROR_OK)
+               return retval;
 
        if (Rd < 15)
        {
                /* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */
-               cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
+               retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
                                &dscr);
+               if (retval != ERROR_OK)
+                       return retval;
        }
        else if (Rd == 15)
        {
                /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
                 * then "mov r15, r0"
                 */
-               cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+               retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
                                &dscr);
-               cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr);
+               if (retval != ERROR_OK)
+                       return retval;
+               retval = cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr);
+               if (retval != ERROR_OK)
+                       return retval;
        }
        else
        {
                /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
                 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
                 */
-               cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+               retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
                                &dscr);
-               cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
+               if (retval != ERROR_OK)
+                       return retval;
+               retval = cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
                                &dscr);
+               if (retval != ERROR_OK)
+                       return retval;
 
                /* "Prefetch flush" after modifying execution status in CPSR */
                if (Rd == 16)
-                       cortex_a8_exec_opcode(target,
+               {
+                       retval = cortex_a8_exec_opcode(target,
                                        ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
                                        &dscr);
+                       if (retval != ERROR_OK)
+                               return retval;
+               }
        }
 
        return retval;
@@ -344,10 +398,14 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
                retval = mem_ap_read_atomic_u32(swjdp,
                                a8->armv7a_common.debug_base + CPUDBG_DSCR,
                                &dscr);
+               if (retval != ERROR_OK)
+                       return retval;
        }
 
        retval = mem_ap_read_atomic_u32(swjdp,
                        a8->armv7a_common.debug_base + CPUDBG_DTRTX, data);
+       if (retval != ERROR_OK)
+               return retval;
        //LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
 
        if (dscr_p)
@@ -364,13 +422,22 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
        int retval;
 
        /* set up invariant:  INSTR_COMP is set after ever DPM operation */
-       do {
+       long long then = timeval_ms();
+       for (;;)
+       {
                retval = mem_ap_read_atomic_u32(swjdp,
                                a8->armv7a_common.debug_base + CPUDBG_DSCR,
                                &dscr);
                if (retval != ERROR_OK)
                        return retval;
-       } while ((dscr & DSCR_INSTR_COMP) == 0);
+               if ((dscr & DSCR_INSTR_COMP) != 0)
+                       break;
+               if (timeval_ms() > then + 1000)
+               {
+                       LOG_ERROR("Timeout waiting for dpm prepare");
+                       return ERROR_FAIL;
+               }
+       }
 
        /* this "should never happen" ... */
        if (dscr & DSCR_DTR_RX_FULL) {
@@ -380,6 +447,8 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
                                a8->armv7a_common.armv4_5_common.target,
                                ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
                                &dscr);
+               if (retval != ERROR_OK)
+                       return retval;
        }
 
        return retval;
@@ -420,6 +489,8 @@ static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
                        a8->armv7a_common.armv4_5_common.target,
                        ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
                        &dscr);
+       if (retval != ERROR_OK)
+               return retval;
 
        /* then the opcode, taking data from R0 */
        retval = cortex_a8_exec_opcode(
@@ -453,6 +524,8 @@ static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
                        a8->armv7a_common.armv4_5_common.target,
                        opcode,
                        &dscr);
+       if (retval != ERROR_OK)
+               return retval;
 
        return cortex_a8_read_dcc(a8, data, &dscr);
 }
@@ -470,12 +543,16 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
                        a8->armv7a_common.armv4_5_common.target,
                        opcode,
                        &dscr);
+       if (retval != ERROR_OK)
+               return retval;
 
        /* write R0 to DCC */
        retval = cortex_a8_exec_opcode(
                        a8->armv7a_common.armv4_5_common.target,
                        ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
                        &dscr);
+       if (retval != ERROR_OK)
+               return retval;
 
        return cortex_a8_read_dcc(a8, data, &dscr);
 }
@@ -668,12 +745,23 @@ static int cortex_a8_halt(struct target *target)
        if (retval != ERROR_OK)
                goto out;
 
-       do {
+       long long then = timeval_ms();
+       for (;;)
+       {
                retval = mem_ap_read_atomic_u32(swjdp,
                        armv7a->debug_base + CPUDBG_DSCR, &dscr);
                if (retval != ERROR_OK)
                        goto out;
-       } while ((dscr & DSCR_CORE_HALTED) == 0);
+               if ((dscr & DSCR_CORE_HALTED) != 0)
+               {
+                       break;
+               }
+               if (timeval_ms() > then + 1000)
+               {
+                       LOG_ERROR("Timeout waiting for halt");
+                       return ERROR_FAIL;
+               }
+       }
 
        target->debug_reason = DBG_REASON_DBGRQ;
 
@@ -776,12 +864,21 @@ static int cortex_a8_resume(struct target *target, int current,
        if (retval != ERROR_OK)
                return retval;
 
-       do {
+       long long then = timeval_ms();
+       for (;;)
+       {
                retval = mem_ap_read_atomic_u32(swjdp,
                        armv7a->debug_base + CPUDBG_DSCR, &dscr);
                if (retval != ERROR_OK)
                        return retval;
-       } while ((dscr & DSCR_CORE_RESTARTED) == 0);
+               if ((dscr & DSCR_CORE_RESTARTED) != 0)
+                       break;
+               if (timeval_ms() > then + 1000)
+               {
+                       LOG_ERROR("Timeout waiting for resume");
+                       return ERROR_FAIL;
+               }
+       }
 
        target->debug_reason = DBG_REASON_NOTHALTED;
        target->state = TARGET_RUNNING;
@@ -874,7 +971,9 @@ static int cortex_a8_debug_entry(struct target *target)
                target_free_working_area(target, regfile_working_area);
 
                /* read Current PSR */
-               cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
+               retval = cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
+               if (retval != ERROR_OK)
+                       return retval;
                dap_ap_select(swjdp, swjdp_debugap);
                LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
 
@@ -975,6 +1074,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
        struct breakpoint *breakpoint = NULL;
        struct breakpoint stepbreakpoint;
        struct reg *r;
+       int retval;
 
        int timeout = 100;
 
@@ -1018,15 +1118,19 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 
        target->debug_reason = DBG_REASON_SINGLESTEP;
 
-       cortex_a8_resume(target, 1, address, 0, 0);
+       retval = cortex_a8_resume(target, 1, address, 0, 0);
+       if (retval != ERROR_OK)
+               return retval;
 
        while (target->state != TARGET_HALTED)
        {
-               cortex_a8_poll(target);
+               retval = cortex_a8_poll(target);
+               if (retval != ERROR_OK)
+                       return retval;
                if (--timeout == 0)
                {
-                       LOG_WARNING("timeout waiting for target halt");
-                       break;
+                       LOG_ERROR("timeout waiting for target halt");
+                       return ERROR_FAIL;
                }
        }
 
@@ -1059,7 +1163,7 @@ static int cortex_a8_restore_context(struct target *target, bool bpwp)
 
 
 /*
- * Cortex-A8 Breakpoint and watchpoint fuctions
+ * Cortex-A8 Breakpoint and watchpoint functions
  */
 
 /* Setup hardware Breakpoint Register Pair */
@@ -1219,7 +1323,7 @@ static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint
        struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
 
 #if 0
-/* It is perfectly possible to remove brakpoints while the taget is running */
+/* It is perfectly possible to remove breakpoints while the target is running */
        if (target->state != TARGET_HALTED)
        {
                LOG_WARNING("target not halted");
@@ -1241,7 +1345,7 @@ static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint
 
 
 /*
- * Cortex-A8 Reset fuctions
+ * Cortex-A8 Reset functions
  */
 
 static int cortex_a8_assert_reset(struct target *target)
@@ -1283,6 +1387,8 @@ static int cortex_a8_deassert_reset(struct target *target)
        jtag_add_reset(0, 0);
 
        retval = cortex_a8_poll(target);
+       if (retval != ERROR_OK)
+               return retval;
 
        if (target->reset_halt) {
                if (target->state != TARGET_HALTED) {
@@ -1337,12 +1443,16 @@ static int cortex_a8_read_memory(struct target *target, uint32_t address,
 {
         int enabled = 0;
         uint32_t virt, phys;
+        int retval;
 
        /* cortex_a8 handles unaligned memory access */
 
 // ??? dap_ap_select(swjdp, swjdp_memoryap);
         LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, size, count);
-        cortex_a8_mmu(target, &enabled);
+        retval = cortex_a8_mmu(target, &enabled);
+        if (retval != ERROR_OK)
+               return retval;
+
         if(enabled)
         {
             virt = address;
@@ -1440,11 +1550,14 @@ static int cortex_a8_write_memory(struct target *target, uint32_t address,
 {
         int enabled = 0;
         uint32_t virt, phys;
+        int retval;
 
 // ???  dap_ap_select(swjdp, swjdp_memoryap);
 
         LOG_DEBUG("Writing memory to address 0x%x; size %d; count %d", address, size, count);
-        cortex_a8_mmu(target, &enabled);
+        retval = cortex_a8_mmu(target, &enabled);
+        if (retval != ERROR_OK)
+               return retval;
         if(enabled)
         {
             virt = address;
@@ -1752,7 +1865,7 @@ static uint32_t cortex_a8_get_ttb(struct target *target)
                     2, 0,   /* CRn, CRm */
                     &ttb);
     }
-    /* finaly we don't know whose ttb to use: user or kernel */
+    /* finally we don't know whose ttb to use: user or kernel */
     else
         LOG_ERROR("Don't know how to get ttb for current mode!!!");
 
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