static int cortex_a8_mmu(struct target *target, int *enabled);
static int cortex_a8_virt2phys(struct target *target,
uint32_t virt, uint32_t *phys);
-static void cortex_a8_disable_mmu_caches(struct target *target, int mmu,
+static int cortex_a8_disable_mmu_caches(struct target *target, int mmu,
int d_u_cache, int i_cache);
-static void cortex_a8_enable_mmu_caches(struct target *target, int mmu,
+static int cortex_a8_enable_mmu_caches(struct target *target, int mmu,
int d_u_cache, int i_cache);
-static uint32_t cortex_a8_get_ttb(struct target *target);
+static int cortex_a8_get_ttb(struct target *target, uint32_t *result);
/*
LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
/* Wait for InstrCompl bit to be set */
+ long long then = timeval_ms();
while ((dscr & DSCR_INSTR_COMP) == 0)
{
retval = mem_ap_read_atomic_u32(swjdp,
LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
return retval;
}
+ if (timeval_ms() > then + 1000)
+ {
+ LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
+ return ERROR_FAIL;
+ }
}
retval = mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
if (retval != ERROR_OK)
return retval;
+ then = timeval_ms();
do
{
retval = mem_ap_read_atomic_u32(swjdp,
LOG_ERROR("Could not read DSCR register");
return retval;
}
+ if (timeval_ms() > then + 1000)
+ {
+ LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
+ return ERROR_FAIL;
+ }
}
while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */
}
/* Wait for DTRRXfull then read DTRRTX */
+ long long then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) == 0)
{
retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
+ if (timeval_ms() > then + 1000)
+ {
+ LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
+ return ERROR_FAIL;
+ }
}
retval = mem_ap_read_atomic_u32(swjdp,
dscr = *dscr_p;
/* Wait for DTRRXfull */
+ long long then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) == 0) {
retval = mem_ap_read_atomic_u32(swjdp,
a8->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
if (retval != ERROR_OK)
return retval;
+ if (timeval_ms() > then + 1000)
+ {
+ LOG_ERROR("Timeout waiting for read dcc");
+ return ERROR_FAIL;
+ }
}
retval = mem_ap_read_atomic_u32(swjdp,
/* Are we in an exception handler */
// armv4_5->exception_number = 0;
if (armv7a->post_debug_entry)
- armv7a->post_debug_entry(target);
+ {
+ retval = armv7a->post_debug_entry(target);
+ if (retval != ERROR_OK)
+ return retval;
+ }
return retval;
}
-static void cortex_a8_post_debug_entry(struct target *target)
+static int cortex_a8_post_debug_entry(struct target *target)
{
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
0, 0, /* op1, op2 */
1, 0, /* CRn, CRm */
&cortex_a8->cp15_control_reg);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg);
if (armv7a->armv4_5_mmu.armv4_5_cache.ctype == -1)
0, 1, /* op1, op2 */
0, 0, /* CRn, CRm */
&cache_type_reg);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("cp15 cache type: %8.8x", (unsigned) cache_type_reg);
/* FIXME the armv4_4 cache info DOES NOT APPLY to Cortex-A8 */
armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
(cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0;
-
+ return ERROR_OK;
}
static int cortex_a8_step(struct target *target, int current, uint32_t address,
struct reg *r;
int retval;
- int timeout = 100;
-
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
if (retval != ERROR_OK)
return retval;
+ long long then = timeval_ms();
while (target->state != TARGET_HALTED)
{
retval = cortex_a8_poll(target);
if (retval != ERROR_OK)
return retval;
- if (--timeout == 0)
+ if (timeval_ms() > then + 1000)
{
LOG_ERROR("timeout waiting for target halt");
return ERROR_FAIL;
}
cortex_a8_unset_breakpoint(target, &stepbreakpoint);
- if (timeout > 0)
- target->debug_reason = DBG_REASON_BREAKPOINT;
+
+ target->debug_reason = DBG_REASON_BREAKPOINT;
if (breakpoint)
cortex_a8_set_breakpoint(target, breakpoint, 0);
if (brp_i >= cortex_a8->brp_num)
{
LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
- return ERROR_FAIL;
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
breakpoint->set = brp_i + 1;
if (breakpoint->length == 2)
if (breakpoint->type == BKPT_HARD)
cortex_a8->brp_num_available--;
- cortex_a8_set_breakpoint(target, breakpoint, 0x00); /* Exact match */
- return ERROR_OK;
+ return cortex_a8_set_breakpoint(target, breakpoint, 0x00); /* Exact match */
}
static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
return cortex_a8_init_arch_info(target, cortex_a8, target->tap);
}
-/* FIX! error propagation missing from this fn */
-static uint32_t cortex_a8_get_ttb(struct target *target)
+static int cortex_a8_get_ttb(struct target *target, uint32_t *result)
{
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
0, 1, /* op1, op2 */
2, 0, /* CRn, CRm */
&ttb);
+ if (retval != ERROR_OK)
+ return retval;
}
else if(cortex_a8->current_address_mode == ARM_MODE_USR)
{
0, 0, /* op1, op2 */
2, 0, /* CRn, CRm */
&ttb);
+ if (retval != ERROR_OK)
+ return retval;
}
/* we don't know whose address is: user or kernel
we assume that if we are in kernel mode then
0, 1, /* op1, op2 */
2, 0, /* CRn, CRm */
&ttb);
+ if (retval != ERROR_OK)
+ return retval;
}
else if(armv7a->armv4_5_common.core_mode == ARM_MODE_USR)
{
0, 0, /* op1, op2 */
2, 0, /* CRn, CRm */
&ttb);
+ if (retval != ERROR_OK)
+ return retval;
}
/* finally we don't know whose ttb to use: user or kernel */
else
ttb &= 0xffffc000;
- return ttb;
+ *result = ttb;
+
+ return ERROR_OK;
}
-/* FIX! error propagation missing from this fn */
-static void cortex_a8_disable_mmu_caches(struct target *target, int mmu,
+static int cortex_a8_disable_mmu_caches(struct target *target, int mmu,
int d_u_cache, int i_cache)
{
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
uint32_t cp15_control;
+ int retval;
/* read cp15 control register */
- armv7a->armv4_5_common.mrc(target, 15,
+ retval = armv7a->armv4_5_common.mrc(target, 15,
0, 0, /* op1, op2 */
1, 0, /* CRn, CRm */
&cp15_control);
+ if (retval != ERROR_OK)
+ return retval;
if (mmu)
if (i_cache)
cp15_control &= ~0x1000U;
- armv7a->armv4_5_common.mcr(target, 15,
+ retval = armv7a->armv4_5_common.mcr(target, 15,
0, 0, /* op1, op2 */
1, 0, /* CRn, CRm */
cp15_control);
+ return retval;
}
-/* FIX! error propagation missing from this fn */
-static void cortex_a8_enable_mmu_caches(struct target *target, int mmu,
+static int cortex_a8_enable_mmu_caches(struct target *target, int mmu,
int d_u_cache, int i_cache)
{
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
uint32_t cp15_control;
+ int retval;
/* read cp15 control register */
- armv7a->armv4_5_common.mrc(target, 15,
+ retval = armv7a->armv4_5_common.mrc(target, 15,
0, 0, /* op1, op2 */
1, 0, /* CRn, CRm */
&cp15_control);
+ if (retval != ERROR_OK)
+ return retval;
if (mmu)
cp15_control |= 0x1U;
if (i_cache)
cp15_control |= 0x1000U;
- armv7a->armv4_5_common.mcr(target, 15,
+ retval = armv7a->armv4_5_common.mcr(target, 15,
0, 0, /* op1, op2 */
1, 0, /* CRn, CRm */
cp15_control);
+ return retval;
}