int cortex_a8_assert_reset(target_t *target);
int cortex_a8_deassert_reset(target_t *target);
+static int cortex_a8_mrc(target_t *target, int cpnum, uint32_t op1,
+ uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value);
+static int cortex_a8_mcr(target_t *target, int cpnum, uint32_t op1,
+ uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value);
+
target_type_t cortexa8_target =
{
.name = "cortex_a8",
.target_create = cortex_a8_target_create,
.init_target = cortex_a8_init_target,
.examine = cortex_a8_examine,
- .quit = NULL
+ .mrc = cortex_a8_mrc,
+ .mcr = cortex_a8_mcr,
};
/*
return cortex_a8_write_cp(target, value, 15, op1, CRn, CRm, op2);
}
+static int cortex_a8_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
+{
+ if (cpnum!=15)
+ {
+ LOG_ERROR("Only cp15 is supported");
+ return ERROR_FAIL;
+ }
+ return cortex_a8_read_cp15(target, op1, op2, CRn, CRm, value);
+}
+
+static int cortex_a8_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+{
+ if (cpnum!=15)
+ {
+ LOG_ERROR("Only cp15 is supported");
+ return ERROR_FAIL;
+ }
+ return cortex_a8_write_cp15(target, op1, op2, CRn, CRm, value);
+}
+
+
+
int cortex_a8_dap_read_coreregister_u32(target_t *target,
uint32_t *value, int regnum)
{
cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
swjdp_common_t *swjdp = &armv7a->swjdp_info;
- if (armv7a->pre_debug_entry)
- armv7a->pre_debug_entry(target);
-
LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
/* Enable the ITR execution once we are in debug mode */
/* register arch-specific functions */
armv7a->examine_debug_reason = NULL;
- armv7a->pre_debug_entry = NULL;
armv7a->post_debug_entry = cortex_a8_post_debug_entry;
armv7a->pre_restore_context = NULL;