return retval;
}
-int cortex_a8_exec_opcode(struct target *target, uint32_t opcode)
+/* FIXME we waste a *LOT* of round-trips with needless DSCR reads, which
+ * slows down operations considerably. One good way to start reducing
+ * them would pass current values into and out of this routine. That
+ * should also help synch DCC read/write.
+ */
+static int cortex_a8_exec_opcode(struct target *target, uint32_t opcode)
{
uint32_t dscr;
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct swjdp_common *swjdp = &armv7a->swjdp_info;
- if (reg > 16)
+ if (reg > 17)
return retval;
if (reg < 15)
cortex_a8_exec_opcode(target, 0xE1A0000F);
cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
}
- else if (reg == 16)
+ else
{
- /* "MRS r0, CPSR"; then move r0 to DCCTX */
- cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, 0));
+ /* "MRS r0, CPSR" or "MRS r0, SPSR"
+ * then move r0 to DCCTX
+ */
+ cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1));
cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
}
retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DTRTX, value);
+ LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
return retval;
}
-static int cortex_a8_dap_write_coreregister_u32(struct target *target, uint32_t value, int regnum)
+static int cortex_a8_dap_write_coreregister_u32(struct target *target,
+ uint32_t value, int regnum)
{
int retval = ERROR_OK;
uint8_t Rd = regnum&0xFF;
cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
}
- if (Rd > 16)
+ if (Rd > 17)
return retval;
/* Write to DCCRX */
+ LOG_DEBUG("write DCC 0x%08" PRIx32, value);
retval = mem_ap_write_u32(swjdp,
armv7a->debug_base + CPUDBG_DTRRX, value);
if (Rd < 15)
{
- /* DCCRX to Rd, MCR p14, 0, Rd, c0, c5, 0, 0xEE000E15 */
+ /* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */
cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0));
}
else if (Rd == 15)
{
+ /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
+ * then "mov r15, r0"
+ */
cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
cortex_a8_exec_opcode(target, 0xE1A0F000);
}
- else if (Rd == 16)
+ else
{
+ /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
+ * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
+ */
cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
- cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, 0));
- /* Execute a PrefetchFlush instruction through the ITR. */
- cortex_a8_exec_opcode(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
+ cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1));
+
+ /* "Prefetch flush" after modifying execution status in CPSR */
+ if (Rd == 16)
+ cortex_a8_exec_opcode(target,
+ ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
}
return retval;
return retval;
}
+/*
+ * Cortex-A8 implementation of Debug Programmer's Model
+ *
+ * NOTE that in several of these cases the "stall" mode might be useful.
+ * It'd let us queue a few operations together... prepare/finish might
+ * be the places to enable/disable that mode.
+ */
+
+static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm)
+{
+ return container_of(dpm, struct cortex_a8_common, armv7a_common.dpm);
+}
+
+static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data)
+{
+ LOG_DEBUG("write DCC 0x%08" PRIx32, data);
+ return mem_ap_write_u32(&a8->armv7a_common.swjdp_info,
+ a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
+}
+
+static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data)
+{
+ struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
+ uint32_t dscr;
+ int retval;
+
+ /* Wait for DTRRXfull */
+ do {
+ retval = mem_ap_read_atomic_u32(swjdp,
+ a8->armv7a_common.debug_base + CPUDBG_DSCR,
+ &dscr);
+ } while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0);
+
+ retval = mem_ap_read_atomic_u32(swjdp,
+ a8->armv7a_common.debug_base + CPUDBG_DTRTX, data);
+ LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
+
+ return retval;
+}
+
+static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
+ uint32_t dscr;
+ int retval;
+
+ retval = mem_ap_read_atomic_u32(swjdp,
+ a8->armv7a_common.debug_base + CPUDBG_DSCR,
+ &dscr);
+
+ /* this "should never happen" ... */
+ if (dscr & (1 << DSCR_DTR_RX_FULL)) {
+ LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
+ /* Clear DCCRX */
+ retval = cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
+ }
+
+ return retval;
+}
+
+static int cortex_a8_dpm_finish(struct arm_dpm *dpm)
+{
+ /* REVISIT what could be done here? */
+ return ERROR_OK;
+}
+
+static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm,
+ uint32_t opcode, uint32_t data)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ int retval;
+
+ retval = cortex_a8_write_dcc(a8, data);
+
+ return cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ opcode);
+}
+
+static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
+ uint32_t opcode, uint32_t data)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ int retval;
+
+ retval = cortex_a8_write_dcc(a8, data);
+
+ /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
+ retval = cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
+
+ /* then the opcode, taking data from R0 */
+ retval = cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ opcode);
+
+ return retval;
+}
+
+static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm)
+{
+ struct target *target = dpm->arm->target;
+
+ /* "Prefetch flush" after modifying execution status in CPSR */
+ return cortex_a8_exec_opcode(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
+}
+
+static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
+ uint32_t opcode, uint32_t *data)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ int retval;
+
+ /* the opcode, writing data to DCC */
+ retval = cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ opcode);
+
+ return cortex_a8_read_dcc(a8, data);
+}
+
+
+static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
+ uint32_t opcode, uint32_t *data)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ int retval;
+
+ /* the opcode, writing data to R0 */
+ retval = cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ opcode);
+
+ /* write R0 to DCC */
+ retval = cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
+
+ return cortex_a8_read_dcc(a8, data);
+}
+
+// static
+int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
+{
+ struct arm_dpm *dpm = &a8->armv7a_common.dpm;
+
+ dpm->arm = &a8->armv7a_common.armv4_5_common;
+ dpm->didr = didr;
+
+ dpm->prepare = cortex_a8_dpm_prepare;
+ dpm->finish = cortex_a8_dpm_finish;
+
+ dpm->instr_write_data_dcc = cortex_a8_instr_write_data_dcc;
+ dpm->instr_write_data_r0 = cortex_a8_instr_write_data_r0;
+ dpm->instr_cpsr_sync = cortex_a8_instr_cpsr_sync;
+
+ dpm->instr_read_data_dcc = cortex_a8_instr_read_data_dcc;
+ dpm->instr_read_data_r0 = cortex_a8_instr_read_data_r0;
+
+ return arm_dpm_setup(dpm);
+}
+
+
/*
* Cortex-A8 Run control
*/
uint32_t address, int handle_breakpoints, int debug_execution)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+ struct arm *armv4_5 = &armv7a->armv4_5_common;
struct swjdp_common *swjdp = &armv7a->swjdp_info;
// struct breakpoint *breakpoint = NULL;
/* current = 1: continue on current pc, otherwise continue at <address> */
resume_pc = buf_get_u32(
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 15).value,
+ armv4_5->core_cache->reg_list[15].value,
0, 32);
if (!current)
resume_pc = address;
return ERROR_FAIL;
}
LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 15).value,
+ buf_set_u32(armv4_5->core_cache->reg_list[15].value,
0, 32, resume_pc);
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 15).dirty = 1;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 15).valid = 1;
+ armv4_5->core_cache->reg_list[15].dirty = 1;
+ armv4_5->core_cache->reg_list[15].valid = 1;
cortex_a8_restore_context(target);
-// arm7_9_restore_context(target); TODO Context is currently NOT Properly restored
+
#if 0
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints)
target->state = TARGET_RUNNING;
/* registers are now invalid */
- armv4_5_invalidate_core_regs(target);
+ register_cache_invalidate(armv4_5->core_cache);
if (!debug_execution)
{
struct working_area *regfile_working_area = NULL;
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+ struct arm *armv4_5 = &armv7a->armv4_5_common;
struct swjdp_common *swjdp = &armv7a->swjdp_info;
struct reg *reg;
/* Enable the ITR execution once we are in debug mode */
mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
+
+ /* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
+ * imprecise data aborts get discarded by issuing a Data
+ * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
+ */
+
dscr |= (1 << DSCR_EXT_INT_EN);
retval = mem_ap_write_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, dscr);
/* Examine debug reason */
switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
{
- case 0:
- case 4:
+ case 0: /* DRCR[0] write */
+ case 4: /* EDBGRQ */
target->debug_reason = DBG_REASON_DBGRQ;
break;
- case 1:
- case 3:
+ case 1: /* HW breakpoint */
+ case 3: /* SW BKPT */
+ case 5: /* vector catch */
target->debug_reason = DBG_REASON_BREAKPOINT;
break;
- case 10:
+ case 10: /* precise watchpoint */
target->debug_reason = DBG_REASON_WATCHPOINT;
+ /* REVISIT could collect WFAR later, to see just
+ * which instruction triggered the watchpoint.
+ */
break;
default:
target->debug_reason = DBG_REASON_UNDEFINED;
break;
}
+ /* REVISIT fast_reg_read is never set ... */
+
/* Examine target state and mode */
if (cortex_a8->fast_reg_read)
target_alloc_working_area(target, 64, ®file_working_area);
dap_ap_select(swjdp, swjdp_debugap);
LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
- armv4_5->core_mode = cpsr & 0x1F;
-
- i = (cpsr >> 5) & 1; /* T */
- i |= (cpsr >> 23) & 1; /* J << 1 */
- switch (i) {
- case 0: /* J = 0, T = 0 */
- armv4_5->core_state = ARMV4_5_STATE_ARM;
- break;
- case 1: /* J = 0, T = 1 */
- armv4_5->core_state = ARMV4_5_STATE_THUMB;
- break;
- case 2: /* J = 1, T = 0 */
- LOG_WARNING("Jazelle state -- not handled");
- armv4_5->core_state = ARMV4_5_STATE_JAZELLE;
- break;
- case 3: /* J = 1, T = 1 */
- /* ThumbEE is very much like Thumb, but some of the
- * instructions are different. Single stepping and
- * breakpoints need updating...
- */
- LOG_WARNING("ThumbEE -- incomplete support");
- armv4_5->core_state = ARM_STATE_THUMB_EE;
- break;
- }
+ arm_set_cpsr(armv4_5, cpsr);
/* update cache */
- reg = armv4_5->core_cache->reg_list + ARMV4_5_CPSR;
- buf_set_u32(reg->value, 0, 32, cpsr);
- reg->valid = 1;
- reg->dirty = 0;
-
for (i = 0; i <= ARM_PC; i++)
{
- reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, i);
+ reg = arm_reg_current(armv4_5, i);
buf_set_u32(reg->value, 0, 32, regfile[i]);
reg->valid = 1;
// ARM state
regfile[ARM_PC] -= 8;
}
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, ARM_PC).value,
- 0, 32, regfile[ARM_PC]);
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
- .dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 0).valid;
+ reg = armv4_5->core_cache->reg_list + 15;
+ buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
+ reg->dirty = reg->valid;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
.dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, 15).valid;
int handle_breakpoints)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+ struct arm *armv4_5 = &armv7a->armv4_5_common;
struct breakpoint *breakpoint = NULL;
struct breakpoint stepbreakpoint;
+ struct reg *r;
int timeout = 100;
}
/* current = 1: continue on current pc, otherwise continue at <address> */
+ r = armv4_5->core_cache->reg_list + 15;
if (!current)
{
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, ARM_PC).value,
- 0, 32, address);
+ buf_set_u32(r->value, 0, 32, address);
}
else
{
- address = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, ARM_PC).value,
- 0, 32);
+ address = buf_get_u32(r->value, 0, 32);
}
/* The front-end may request us not to handle breakpoints.
*/
handle_breakpoints = 1;
if (handle_breakpoints) {
- breakpoint = breakpoint_find(target,
- buf_get_u32(ARMV4_5_CORE_REG_MODE(
- armv4_5->core_cache,
- armv4_5->core_mode, 15).value,
- 0, 32));
+ breakpoint = breakpoint_find(target, address);
if (breakpoint)
cortex_a8_unset_breakpoint(target, breakpoint);
}
static int cortex_a8_restore_context(struct target *target)
{
- int i;
uint32_t value;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+ struct reg_cache *cache = armv7a->armv4_5_common.core_cache;
+ unsigned max = cache->num_regs;
+ struct reg *r;
+ bool flushed, flush_cpsr = false;
LOG_DEBUG(" ");
if (armv7a->pre_restore_context)
armv7a->pre_restore_context(target);
- for (i = 15; i >= 0; i--)
- {
- if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, i).dirty)
- {
- value = buf_get_u32(ARMV4_5_CORE_REG_MODE(
- armv4_5->core_cache,
- armv4_5->core_mode, i).value,
- 0, 32);
+ /* Flush all dirty registers from the cache, one mode at a time so
+ * that we write CPSR as little as possible. Save CPSR and R0 for
+ * last; they're used to change modes and write other registers.
+ *
+ * REVISIT be smarter: save eventual mode for last loop, don't
+ * need to write CPSR an extra time.
+ */
+ do {
+ enum armv4_5_mode mode = ARMV4_5_MODE_ANY;
+ unsigned i;
+
+ flushed = false;
+
+ /* write dirty non-{R0,CPSR} registers sharing the same mode */
+ for (i = max - 1, r = cache->reg_list + 1; i > 0; i--, r++) {
+ struct arm_reg *reg;
+
+ if (!r->dirty || r == armv7a->armv4_5_common.cpsr)
+ continue;
+ reg = r->arch_info;
+
/* TODO Check return values */
- cortex_a8_dap_write_coreregister_u32(target, value, i);
+
+ /* Pick a mode and update CPSR; else ignore this
+ * register if it's for a different mode than what
+ * we're handling on this pass.
+ *
+ * REVISIT don't distinguish SYS and USR modes.
+ *
+ * FIXME if we restore from FIQ mode, R8..R12 will
+ * get wrongly flushed onto FIQ shadows...
+ */
+ if (mode == ARMV4_5_MODE_ANY) {
+ mode = reg->mode;
+ if (mode != ARMV4_5_MODE_ANY) {
+ cortex_a8_dap_write_coreregister_u32(
+ target, mode, 16);
+ flush_cpsr = true;
+ }
+ } else if (mode != reg->mode)
+ continue;
+
+ /* Write this register */
+ value = buf_get_u32(r->value, 0, 32);
+ cortex_a8_dap_write_coreregister_u32(target, value,
+ (reg->num == 16) ? 17 : reg->num);
+ r->dirty = false;
+ flushed = true;
}
+
+ } while (flushed);
+
+ /* now flush CPSR if needed ... */
+ r = armv7a->armv4_5_common.cpsr;
+ if (flush_cpsr || r->dirty) {
+ value = buf_get_u32(r->value, 0, 32);
+ cortex_a8_dap_write_coreregister_u32(target, value, 16);
+ r->dirty = false;
}
+ /* ... and R0 always (it was dirtied when we saved context) */
+ r = cache->reg_list + 0;
+ value = buf_get_u32(r->value, 0, 32);
+ cortex_a8_dap_write_coreregister_u32(target, value, 0);
+ r->dirty = false;
+
if (armv7a->post_restore_context)
armv7a->post_restore_context(target);
armv4_5_mode_t mode, uint32_t * value)
{
int retval;
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
if ((num <= ARM_CPSR))
{
{
int retval;
// uint32_t reg;
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
#ifdef ARMV7_GDB_HACKS
/* If the LR register is being modified, make sure it will put us
#endif
-static int cortex_a8_read_core_reg(struct target *target, int num,
- enum armv4_5_mode mode)
+static int cortex_a8_write_core_reg(struct target *target, struct reg *r,
+ int num, enum armv4_5_mode mode, uint32_t value);
+
+static int cortex_a8_read_core_reg(struct target *target, struct reg *r,
+ int num, enum armv4_5_mode mode)
{
uint32_t value;
int retval;
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
+ struct reg *cpsr_r = NULL;
+ uint32_t cpsr = 0;
+ unsigned cookie = num;
- /* FIXME cortex may not be in "mode" ... */
-
- cortex_a8_dap_read_coreregister_u32(target, &value, num);
+ /* avoid some needless mode changes
+ * FIXME move some of these to shared ARM code...
+ */
+ if (mode != armv4_5->core_mode) {
+ if ((armv4_5->core_mode == ARMV4_5_MODE_SYS)
+ && (mode == ARMV4_5_MODE_USR))
+ mode = ARMV4_5_MODE_ANY;
+ else if ((mode != ARMV4_5_MODE_FIQ) && (num <= 12))
+ mode = ARMV4_5_MODE_ANY;
+
+ if (mode != ARMV4_5_MODE_ANY) {
+ cpsr_r = armv4_5->cpsr;
+ cpsr = buf_get_u32(cpsr_r->value, 0, 32);
+ cortex_a8_write_core_reg(target, cpsr_r,
+ 16, ARMV4_5_MODE_ANY, mode);
+ }
+ }
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
- return retval;
+ if (num == 16) {
+ switch (mode) {
+ case ARMV4_5_MODE_USR:
+ case ARMV4_5_MODE_SYS:
+ case ARMV4_5_MODE_ANY:
+ /* CPSR */
+ break;
+ default:
+ /* SPSR */
+ cookie++;
+ break;
+ }
}
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- mode, num).value, 0, 32, value);
+ cortex_a8_dap_read_coreregister_u32(target, &value, cookie);
+ retval = jtag_execute_queue();
+ if (retval == ERROR_OK) {
+ r->valid = 1;
+ r->dirty = 0;
+ buf_set_u32(r->value, 0, 32, value);
+ }
- return ERROR_OK;
+ if (cpsr_r)
+ cortex_a8_write_core_reg(target, cpsr_r,
+ 16, ARMV4_5_MODE_ANY, cpsr);
+ return retval;
}
-static int cortex_a8_write_core_reg(struct target *target, int num,
- enum armv4_5_mode mode, uint32_t value)
+static int cortex_a8_write_core_reg(struct target *target, struct reg *r,
+ int num, enum armv4_5_mode mode, uint32_t value)
{
int retval;
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
+ struct reg *cpsr_r = NULL;
+ uint32_t cpsr = 0;
+ unsigned cookie = num;
+
+ /* avoid some needless mode changes
+ * FIXME move some of these to shared ARM code...
+ */
+ if (mode != armv4_5->core_mode) {
+ if ((armv4_5->core_mode == ARMV4_5_MODE_SYS)
+ && (mode == ARMV4_5_MODE_USR))
+ mode = ARMV4_5_MODE_ANY;
+ else if ((mode != ARMV4_5_MODE_FIQ) && (num <= 12))
+ mode = ARMV4_5_MODE_ANY;
+
+ if (mode != ARMV4_5_MODE_ANY) {
+ cpsr_r = armv4_5->cpsr;
+ cpsr = buf_get_u32(cpsr_r->value, 0, 32);
+ cortex_a8_write_core_reg(target, cpsr_r,
+ 16, ARMV4_5_MODE_ANY, mode);
+ }
+ }
- /* FIXME cortex may not be in "mode" ... */
- cortex_a8_dap_write_coreregister_u32(target, value, num);
- if ((retval = jtag_execute_queue()) != ERROR_OK)
- {
- return retval;
+ if (num == 16) {
+ switch (mode) {
+ case ARMV4_5_MODE_USR:
+ case ARMV4_5_MODE_SYS:
+ case ARMV4_5_MODE_ANY:
+ /* CPSR */
+ break;
+ default:
+ /* SPSR */
+ cookie++;
+ break;
+ }
}
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
+ cortex_a8_dap_write_coreregister_u32(target, value, cookie);
+ if ((retval = jtag_execute_queue()) == ERROR_OK) {
+ buf_set_u32(r->value, 0, 32, value);
+ r->valid = 1;
+ r->dirty = 0;
+ }
- return ERROR_OK;
+ if (cpsr_r)
+ cortex_a8_write_core_reg(target, cpsr_r,
+ 16, ARMV4_5_MODE_ANY, cpsr);
+ return retval;
}
return ERROR_OK;
}
-int cortex_a8_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
+static int cortex_a8_add_breakpoint(struct target *target,
+ struct breakpoint *breakpoint)
{
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
static int cortex_a8_assert_reset(struct target *target)
{
+ struct armv7a_common *armv7a = target_to_armv7a(target);
LOG_DEBUG(" ");
/* registers are now invalid */
- armv4_5_invalidate_core_regs(target);
+ register_cache_invalidate(armv7a->armv4_5_common.core_cache);
target->state = TARGET_RESET;
return retval;
}
-int cortex_a8_write_memory(struct target *target, uint32_t address,
+static int cortex_a8_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
static void cortex_a8_build_reg_cache(struct target *target)
{
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_armv4_5(target);
armv4_5->core_type = ARM_MODE_MON;
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
- armv4_5->core_cache = (*cache_p);
}
return ERROR_OK;
}
-int cortex_a8_init_arch_info(struct target *target,
+static int cortex_a8_init_arch_info(struct target *target,
struct cortex_a8_common *cortex_a8, struct jtag_tap *tap)
{
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
/* prepare JTAG information for the new target */
cortex_a8->jtag_info.tap = tap;
cortex_a8->jtag_info.scann_size = 4;
-LOG_DEBUG(" ");
+
swjdp->dp_select_value = -1;
swjdp->ap_csw_value = -1;
swjdp->ap_tar_value = -1;
Code Review / openocd.git / blobdiff