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Cortex-A/R: Add missing timeout for loop polling DSCR & fix timeout types
[openocd.git] / src / target / cortex_a.c
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 0923f880c0c1eccff9bee989eaddd4a9857dc15c..e6e84bdaf72461b3f687293fe4bde678b4172086 100644 (file)
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -106,6 +106,7 @@ static int cortex_a_restore_cp15_control_reg(struct target *target)
 static int cortex_a_prep_memaccess(struct target *target, int phys_access)
 {
        struct armv7a_common *armv7a = target_to_armv7a(target);
+       struct cortex_a_common *cortex_a = target_to_cortex_a(target);
        int mmu_enabled = 0;
 
        if (phys_access == 0) {
@@ -113,6 +114,12 @@ static int cortex_a_prep_memaccess(struct target *target, int phys_access)
                cortex_a_mmu(target, &mmu_enabled);
                if (mmu_enabled)
                        cortex_a_mmu_modify(target, 1);
+               if (cortex_a->dacrfixup_mode == CORTEX_A_DACRFIXUP_ON) {
+                       /* overwrite DACR to all-manager */
+                       armv7a->arm.mcr(target, 15,
+                                       0, 0, 3, 0,
+                                       0xFFFFFFFF);
+               }
        } else {
                cortex_a_mmu(target, &mmu_enabled);
                if (mmu_enabled)
@@ -129,8 +136,15 @@ static int cortex_a_prep_memaccess(struct target *target, int phys_access)
 static int cortex_a_post_memaccess(struct target *target, int phys_access)
 {
        struct armv7a_common *armv7a = target_to_armv7a(target);
+       struct cortex_a_common *cortex_a = target_to_cortex_a(target);
 
        if (phys_access == 0) {
+               if (cortex_a->dacrfixup_mode == CORTEX_A_DACRFIXUP_ON) {
+                       /* restore */
+                       armv7a->arm.mcr(target, 15,
+                                       0, 0, 3, 0,
+                                       cortex_a->cp15_dacr_reg);
+               }
                dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
        } else {
                int mmu_enabled = 0;
@@ -194,11 +208,11 @@ static int cortex_a8_init_debug_access(struct target *target)
 
        /* Unlocking the debug registers for modification
         * The debugport might be uninitialised so try twice */
-       retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
        if (retval != ERROR_OK) {
                /* try again */
-               retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+               retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                                armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
                if (retval == ERROR_OK)
                        LOG_USER(
@@ -226,7 +240,7 @@ static int cortex_a_init_debug_access(struct target *target)
        switch (cortex_part_num) {
        case CORTEX_A7_PARTNUM:
        case CORTEX_A15_PARTNUM:
-               retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+               retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                                                    armv7a->debug_base + CPUDBG_OSLSR,
                                                    &dbg_osreg);
                if (retval != ERROR_OK)
@@ -236,7 +250,7 @@ static int cortex_a_init_debug_access(struct target *target)
 
                if (dbg_osreg & CPUDBG_OSLAR_LK_MASK)
                        /* Unlocking the DEBUG OS registers for modification */
-                       retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+                       retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                                                             armv7a->debug_base + CPUDBG_OSLAR,
                                                             0);
                break;
@@ -252,7 +266,7 @@ static int cortex_a_init_debug_access(struct target *target)
                return retval;
        /* Clear Sticky Power Down status Bit in PRSR to enable access to
           the registers in the Core Power Domain */
-       retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);
        LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR  0x%" PRIx32, target->coreid, dbg_osreg);
 
@@ -260,13 +274,13 @@ static int cortex_a_init_debug_access(struct target *target)
                return retval;
 
        /* Disable cacheline fills and force cache write-through in debug state */
-       retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DSCCR, 0);
        if (retval != ERROR_OK)
                return retval;
 
        /* Disable TLB lookup and refill/eviction in debug state */
-       retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DSMCR, 0);
        if (retval != ERROR_OK)
                return retval;
@@ -285,10 +299,10 @@ static int cortex_a_wait_instrcmpl(struct target *target, uint32_t *dscr, bool f
         * Writes final value of DSCR into *dscr. Pass force to force always
         * reading DSCR at least once. */
        struct armv7a_common *armv7a = target_to_armv7a(target);
-       long long then = timeval_ms();
+       int64_t then = timeval_ms();
        while ((*dscr & DSCR_INSTR_COMP) == 0 || force) {
                force = false;
-               int retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+               int retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                                armv7a->debug_base + CPUDBG_DSCR, dscr);
                if (retval != ERROR_OK) {
                        LOG_ERROR("Could not read DSCR register");
@@ -323,14 +337,14 @@ static int cortex_a_exec_opcode(struct target *target,
        if (retval != ERROR_OK)
                return retval;
 
-       retval = mem_ap_sel_write_u32(armv7a->debug_ap,
+       retval = mem_ap_write_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_ITR, opcode);
        if (retval != ERROR_OK)
                return retval;
 
-       long long then = timeval_ms();
+       int64_t then = timeval_ms();
        do {
-               retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+               retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                                armv7a->debug_base + CPUDBG_DSCR, &dscr);
                if (retval != ERROR_OK) {
                        LOG_ERROR("Could not read DSCR register");
@@ -368,7 +382,7 @@ static int cortex_a_read_regs_through_mem(struct target *target, uint32_t addres
        if (retval != ERROR_OK)
                return retval;
 
-       retval = mem_ap_sel_read_buf(armv7a->memory_ap,
+       retval = mem_ap_read_buf(armv7a->memory_ap,
                        (uint8_t *)(&regfile[1]), 4, 15, address);
 
        return retval;
@@ -417,9 +431,9 @@ static int cortex_a_dap_read_coreregister_u32(struct target *target,
        }
 
        /* Wait for DTRRXfull then read DTRRTX */
-       long long then = timeval_ms();
+       int64_t then = timeval_ms();
        while ((dscr & DSCR_DTR_TX_FULL) == 0) {
-               retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+               retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                                armv7a->debug_base + CPUDBG_DSCR, &dscr);
                if (retval != ERROR_OK)
                        return retval;
@@ -429,7 +443,7 @@ static int cortex_a_dap_read_coreregister_u32(struct target *target,
                }
        }
 
-       retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DTRTX, value);
        LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
 
@@ -447,7 +461,7 @@ static int cortex_a_dap_write_coreregister_u32(struct target *target,
        LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
 
        /* Check that DCCRX is not full */
-       retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DSCR, &dscr);
        if (retval != ERROR_OK)
                return retval;
@@ -465,7 +479,7 @@ static int cortex_a_dap_write_coreregister_u32(struct target *target,
 
        /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
        LOG_DEBUG("write DCC 0x%08" PRIx32, value);
-       retval = mem_ap_sel_write_u32(armv7a->debug_ap,
+       retval = mem_ap_write_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DTRRX, value);
        if (retval != ERROR_OK)
                return retval;
@@ -522,7 +536,7 @@ static int cortex_a_dap_write_memap_register_u32(struct target *target,
        int retval;
        struct armv7a_common *armv7a = target_to_armv7a(target);
 
-       retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap, address, value);
+       retval = mem_ap_write_atomic_u32(armv7a->debug_ap, address, value);
 
        return retval;
 }
@@ -546,7 +560,7 @@ static inline struct cortex_a_common *dpm_to_a(struct arm_dpm *dpm)
 static int cortex_a_write_dcc(struct cortex_a_common *a, uint32_t data)
 {
        LOG_DEBUG("write DCC 0x%08" PRIx32, data);
-       return mem_ap_sel_write_u32(a->armv7a_common.debug_ap,
+       return mem_ap_write_u32(a->armv7a_common.debug_ap,
                        a->armv7a_common.debug_base + CPUDBG_DTRRX, data);
 }
 
@@ -560,9 +574,9 @@ static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data,
                dscr = *dscr_p;
 
        /* Wait for DTRRXfull */
-       long long then = timeval_ms();
+       int64_t then = timeval_ms();
        while ((dscr & DSCR_DTR_TX_FULL) == 0) {
-               retval = mem_ap_sel_read_atomic_u32(a->armv7a_common.debug_ap,
+               retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
                                a->armv7a_common.debug_base + CPUDBG_DSCR,
                                &dscr);
                if (retval != ERROR_OK)
@@ -573,7 +587,7 @@ static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data,
                }
        }
 
-       retval = mem_ap_sel_read_atomic_u32(a->armv7a_common.debug_ap,
+       retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
                        a->armv7a_common.debug_base + CPUDBG_DTRTX, data);
        if (retval != ERROR_OK)
                return retval;
@@ -592,9 +606,9 @@ static int cortex_a_dpm_prepare(struct arm_dpm *dpm)
        int retval;
 
        /* set up invariant:  INSTR_COMP is set after ever DPM operation */
-       long long then = timeval_ms();
+       int64_t then = timeval_ms();
        for (;; ) {
-               retval = mem_ap_sel_read_atomic_u32(a->armv7a_common.debug_ap,
+               retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
                                a->armv7a_common.debug_base + CPUDBG_DSCR,
                                &dscr);
                if (retval != ERROR_OK)
@@ -881,7 +895,7 @@ static int cortex_a_poll(struct target *target)
                target_call_event_callbacks(target, TARGET_EVENT_HALTED);
                return retval;
        }
-       retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DSCR, &dscr);
        if (retval != ERROR_OK)
                return retval;
@@ -942,7 +956,7 @@ static int cortex_a_halt(struct target *target)
         * Tell the core to be halted by writing DRCR with 0x1
         * and then wait for the core to be halted.
         */
-       retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DRCR, DRCR_HALT);
        if (retval != ERROR_OK)
                return retval;
@@ -950,19 +964,19 @@ static int cortex_a_halt(struct target *target)
        /*
         * enter halting debug mode
         */
-       retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DSCR, &dscr);
        if (retval != ERROR_OK)
                return retval;
 
-       retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
        if (retval != ERROR_OK)
                return retval;
 
-       long long then = timeval_ms();
+       int64_t then = timeval_ms();
        for (;; ) {
-               retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+               retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                                armv7a->debug_base + CPUDBG_DSCR, &dscr);
                if (retval != ERROR_OK)
                        return retval;
@@ -1040,6 +1054,7 @@ static int cortex_a_internal_restore(struct target *target, int current,
        buf_set_u32(arm->pc->value, 0, 32, resume_pc);
        arm->pc->dirty = 1;
        arm->pc->valid = 1;
+
        /* restore dpm_mode at system halt */
        dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
        /* called it now before restoring context because it uses cpu
@@ -1087,7 +1102,7 @@ static int cortex_a_internal_restart(struct target *target)
         * disable IRQs by default, with optional override...
         */
 
-       retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DSCR, &dscr);
        if (retval != ERROR_OK)
                return retval;
@@ -1095,20 +1110,20 @@ static int cortex_a_internal_restart(struct target *target)
        if ((dscr & DSCR_INSTR_COMP) == 0)
                LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
 
-       retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN);
        if (retval != ERROR_OK)
                return retval;
 
-       retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DRCR, DRCR_RESTART |
                        DRCR_CLEAR_EXCEPTIONS);
        if (retval != ERROR_OK)
                return retval;
 
-       long long then = timeval_ms();
+       int64_t then = timeval_ms();
        for (;; ) {
-               retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+               retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                                armv7a->debug_base + CPUDBG_DSCR, &dscr);
                if (retval != ERROR_OK)
                        return retval;
@@ -1199,7 +1214,7 @@ static int cortex_a_debug_entry(struct target *target)
        LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a->cpudbg_dscr);
 
        /* REVISIT surely we should not re-read DSCR !! */
-       retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DSCR, &dscr);
        if (retval != ERROR_OK)
                return retval;
@@ -1211,7 +1226,7 @@ static int cortex_a_debug_entry(struct target *target)
 
        /* Enable the ITR execution once we are in debug mode */
        dscr |= DSCR_ITR_EN;
-       retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DSCR, dscr);
        if (retval != ERROR_OK)
                return retval;
@@ -1223,7 +1238,7 @@ static int cortex_a_debug_entry(struct target *target)
        if (target->debug_reason == DBG_REASON_WATCHPOINT) {
                uint32_t wfar;
 
-               retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+               retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                                armv7a->debug_base + CPUDBG_WFAR,
                                &wfar);
                if (retval != ERROR_OK)
@@ -1336,6 +1351,16 @@ static int cortex_a_post_debug_entry(struct target *target)
                (cortex_a->cp15_control_reg & 0x1000U) ? 1 : 0;
        cortex_a->curr_mode = armv7a->arm.core_mode;
 
+       /* switch to SVC mode to read DACR */
+       dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
+       armv7a->arm.mrc(target, 15,
+                       0, 0, 3, 0,
+                       &cortex_a->cp15_dacr_reg);
+
+       LOG_DEBUG("cp15_dacr_reg: %8.8" PRIx32,
+                       cortex_a->cp15_dacr_reg);
+
+       dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
        return ERROR_OK;
 }
 
@@ -1345,7 +1370,7 @@ int cortex_a_set_dscr_bits(struct target *target, unsigned long bit_mask, unsign
        uint32_t dscr;
 
        /* Read DSCR */
-       int retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+       int retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DSCR, &dscr);
        if (ERROR_OK != retval)
                return retval;
@@ -1356,7 +1381,7 @@ int cortex_a_set_dscr_bits(struct target *target, unsigned long bit_mask, unsign
        dscr |= value & bit_mask;
 
        /* write new DSCR */
-       retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DSCR, dscr);
        return retval;
 }
@@ -1418,7 +1443,7 @@ static int cortex_a_step(struct target *target, int current, uint32_t address,
        if (retval != ERROR_OK)
                return retval;
 
-       long long then = timeval_ms();
+       int64_t then = timeval_ms();
        while (target->state != TARGET_HALTED) {
                retval = cortex_a_poll(target);
                if (retval != ERROR_OK)
@@ -1937,7 +1962,7 @@ static int cortex_a_set_dcc_mode(struct target *target, uint32_t mode, uint32_t
        uint32_t new_dscr = (*dscr & ~DSCR_EXT_DCC_MASK) | mode;
        if (new_dscr != *dscr) {
                struct armv7a_common *armv7a = target_to_armv7a(target);
-               int retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+               int retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                                armv7a->debug_base + CPUDBG_DSCR, new_dscr);
                if (retval == ERROR_OK)
                        *dscr = new_dscr;
@@ -1952,11 +1977,11 @@ static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask,
 {
        /* Waits until the specified bit(s) of DSCR take on a specified value. */
        struct armv7a_common *armv7a = target_to_armv7a(target);
-       long long then = timeval_ms();
+       int64_t then = timeval_ms();
        int retval;
 
        while ((*dscr & mask) != value) {
-               retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+               retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                                armv7a->debug_base + CPUDBG_DSCR, dscr);
                if (retval != ERROR_OK)
                        return retval;
@@ -1994,7 +2019,7 @@ static int cortex_a_read_copro(struct target *target, uint32_t opcode,
                return retval;
 
        /* Read the value transferred to DTRTX. */
-       retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DTRTX, data);
        if (retval != ERROR_OK)
                return retval;
@@ -2029,7 +2054,7 @@ static int cortex_a_write_copro(struct target *target, uint32_t opcode,
        struct armv7a_common *armv7a = target_to_armv7a(target);
 
        /* Write the value into DTRRX. */
-       retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DTRRX, data);
        if (retval != ERROR_OK)
                return retval;
@@ -2132,7 +2157,7 @@ static int cortex_a_write_apb_ab_memory_slow(struct target *target,
                        data = target_buffer_get_u16(target, buffer);
                else
                        data = target_buffer_get_u32(target, buffer);
-               retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+               retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                                armv7a->debug_base + CPUDBG_DTRRX, data);
                if (retval != ERROR_OK)
                        return retval;
@@ -2192,13 +2217,13 @@ static int cortex_a_write_apb_ab_memory_fast(struct target *target,
                return retval;
 
        /* Latch STC instruction. */
-       retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_ITR, ARMV4_5_STC(0, 1, 0, 1, 14, 5, 0, 4));
        if (retval != ERROR_OK)
                return retval;
 
        /* Transfer all the data and issue all the instructions. */
-       return mem_ap_sel_write_buf_noincr(armv7a->debug_ap, buffer,
+       return mem_ap_write_buf_noincr(armv7a->debug_ap, buffer,
                        4, count, armv7a->debug_base + CPUDBG_DTRRX);
 }
 
@@ -2223,13 +2248,13 @@ static int cortex_a_write_apb_ab_memory(struct target *target,
                return ERROR_OK;
 
        /* Clear any abort. */
-       retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
        if (retval != ERROR_OK)
                return retval;
 
        /* Read DSCR. */
-       retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DSCR, &dscr);
        if (retval != ERROR_OK)
                return retval;
@@ -2248,7 +2273,7 @@ static int cortex_a_write_apb_ab_memory(struct target *target,
                goto out;
 
        /* Get the memory address into R0. */
-       retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DTRRX, address);
        if (retval != ERROR_OK)
                goto out;
@@ -2280,7 +2305,7 @@ out:
        /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
         * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
         * check RXfull_l). Most of the time this will be free because RXfull_l
-        * will be cleared immediately and cached in dscr. However, don’t do this
+        * will be cleared immediately and cached in dscr. However, don't do this
         * if there is fault, because then the instruction might not have completed
         * successfully. */
        if (!(dscr & DSCR_STICKY_ABORT_PRECISE)) {
@@ -2292,7 +2317,7 @@ out:
        /* If there were any sticky abort flags, clear them. */
        if (dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE)) {
                fault_dscr = dscr;
-               mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+               mem_ap_write_atomic_u32(armv7a->debug_ap,
                                armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
                dscr &= ~(DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE);
        } else {
@@ -2326,7 +2351,7 @@ out:
        /* If the DCC is nonempty, clear it. */
        if (dscr & DSCR_DTRTX_FULL_LATCHED) {
                uint32_t dummy;
-               retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+               retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                                armv7a->debug_base + CPUDBG_DTRTX, &dummy);
                if (final_retval == ERROR_OK)
                        final_retval = retval;
@@ -2398,7 +2423,7 @@ static int cortex_a_read_apb_ab_memory_slow(struct target *target,
                        return retval;
 
                /* Read the value transferred to DTRTX into the buffer. */
-               retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+               retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                                armv7a->debug_base + CPUDBG_DTRTX, &data);
                if (retval != ERROR_OK)
                        return retval;
@@ -2450,7 +2475,7 @@ static int cortex_a_read_apb_ab_memory_fast(struct target *target,
                        return retval;
 
                /* Latch LDC instruction. */
-               retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+               retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                                armv7a->debug_base + CPUDBG_ITR, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4));
                if (retval != ERROR_OK)
                        return retval;
@@ -2461,7 +2486,7 @@ static int cortex_a_read_apb_ab_memory_fast(struct target *target,
                 * memory. The last read of DTRTX in this call reads the second-to-last
                 * word from memory and issues the read instruction for the last word.
                 */
-               retval = mem_ap_sel_read_buf_noincr(armv7a->debug_ap, buffer,
+               retval = mem_ap_read_buf_noincr(armv7a->debug_ap, buffer,
                                4, count, armv7a->debug_base + CPUDBG_DTRTX);
                if (retval != ERROR_OK)
                        return retval;
@@ -2495,7 +2520,7 @@ static int cortex_a_read_apb_ab_memory_fast(struct target *target,
 
        /* Read the value transferred to DTRTX into the buffer. This is the last
         * word. */
-       retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DTRTX, &u32);
        if (retval != ERROR_OK)
                return retval;
@@ -2525,13 +2550,13 @@ static int cortex_a_read_apb_ab_memory(struct target *target,
                return ERROR_OK;
 
        /* Clear any abort. */
-       retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
        if (retval != ERROR_OK)
                return retval;
 
        /* Read DSCR */
-       retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DSCR, &dscr);
        if (retval != ERROR_OK)
                return retval;
@@ -2550,7 +2575,7 @@ static int cortex_a_read_apb_ab_memory(struct target *target,
                goto out;
 
        /* Get the memory address into R0. */
-       retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DTRRX, address);
        if (retval != ERROR_OK)
                goto out;
@@ -2582,7 +2607,7 @@ out:
        /* If there were any sticky abort flags, clear them. */
        if (dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE)) {
                fault_dscr = dscr;
-               mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+               mem_ap_write_atomic_u32(armv7a->debug_ap,
                                armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
                dscr &= ~(DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE);
        } else {
@@ -2616,7 +2641,7 @@ out:
        /* If the DCC is nonempty, clear it. */
        if (dscr & DSCR_DTRTX_FULL_LATCHED) {
                uint32_t dummy;
-               retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+               retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                                armv7a->debug_base + CPUDBG_DTRTX, &dummy);
                if (final_retval == ERROR_OK)
                        final_retval = retval;
@@ -2711,7 +2736,7 @@ static int cortex_a_read_memory_ahb(struct target *target, uint32_t address,
        if (!count || !buffer)
                return ERROR_COMMAND_SYNTAX_ERROR;
 
-       retval = mem_ap_sel_read_buf(armv7a->memory_ap, buffer, size, count, address);
+       retval = mem_ap_read_buf(armv7a->memory_ap, buffer, size, count, address);
 
        return retval;
 }
@@ -2792,7 +2817,7 @@ static int cortex_a_write_memory_ahb(struct target *target, uint32_t address,
        if (!count || !buffer)
                return ERROR_COMMAND_SYNTAX_ERROR;
 
-       retval = mem_ap_sel_write_buf(armv7a->memory_ap, buffer, size, count, address);
+       retval = mem_ap_write_buf(armv7a->memory_ap, buffer, size, count, address);
 
        return retval;
 }
@@ -2879,18 +2904,23 @@ static int cortex_a_handle_target_request(void *priv)
        if (target->state == TARGET_RUNNING) {
                uint32_t request;
                uint32_t dscr;
-               retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+               retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                                armv7a->debug_base + CPUDBG_DSCR, &dscr);
 
                /* check if we have data */
+               int64_t then = timeval_ms();
                while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) {
-                       retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+                       retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                                        armv7a->debug_base + CPUDBG_DTRTX, &request);
                        if (retval == ERROR_OK) {
                                target_request(target, request);
-                               retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+                               retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                                                armv7a->debug_base + CPUDBG_DSCR, &dscr);
                        }
+                       if (timeval_ms() > then + 1000) {
+                               LOG_ERROR("Timeout waiting for dtr tx full");
+                               return ERROR_FAIL;
+                       }
                }
        }
 
@@ -2929,6 +2959,8 @@ static int cortex_a_examine_first(struct target *target)
                return retval;
        }
 
+       armv7a->debug_ap->memaccess_tck = 80;
+
        /* Search for the AHB-AB.
         * REVISIT: We should search for AXI-AP as well and make sure the AP's MEMTYPE says it
         * can access system memory. */
@@ -2968,33 +3000,33 @@ static int cortex_a_examine_first(struct target *target)
        } else
                armv7a->debug_base = target->dbgbase;
 
-       retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_CPUID, &cpuid);
        if (retval != ERROR_OK)
                return retval;
 
-       retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_CPUID, &cpuid);
        if (retval != ERROR_OK) {
                LOG_DEBUG("Examine %s failed", "CPUID");
                return retval;
        }
 
-       retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_CTYPR, &ctypr);
        if (retval != ERROR_OK) {
                LOG_DEBUG("Examine %s failed", "CTYPR");
                return retval;
        }
 
-       retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_TTYPR, &ttypr);
        if (retval != ERROR_OK) {
                LOG_DEBUG("Examine %s failed", "TTYPR");
                return retval;
        }
 
-       retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                        armv7a->debug_base + CPUDBG_DIDR, &didr);
        if (retval != ERROR_OK) {
                LOG_DEBUG("Examine %s failed", "DIDR");
@@ -3015,7 +3047,7 @@ static int cortex_a_examine_first(struct target *target)
        if ((cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >> CORTEX_A_MIDR_PARTNUM_SHIFT ==
                CORTEX_A15_PARTNUM) {
 
-               retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+               retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                                                     armv7a->debug_base + CPUDBG_OSLAR,
                                                     0);
 
@@ -3027,7 +3059,7 @@ static int cortex_a_examine_first(struct target *target)
        if ((cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >> CORTEX_A_MIDR_PARTNUM_SHIFT ==
                CORTEX_A7_PARTNUM) {
 
-               retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
+               retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
                                                     armv7a->debug_base + CPUDBG_OSLAR,
                                                     0);
 
@@ -3035,7 +3067,7 @@ static int cortex_a_examine_first(struct target *target)
                        return retval;
 
        }
-       retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
+       retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
                                            armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);
 
        if (retval != ERROR_OK)
@@ -3072,6 +3104,9 @@ static int cortex_a_examine_first(struct target *target)
 
        LOG_DEBUG("Configured %i hw breakpoints", cortex_a->brp_num);
 
+       /* select debug_ap as default */
+       swjdp->apsel = armv7a->debug_ap->ap_num;
+
        target_set_examined(target);
        return ERROR_OK;
 }
@@ -3117,7 +3152,6 @@ static int cortex_a_init_arch_info(struct target *target,
                tap->dap->tap = tap;
        }
 
-       tap->dap->ap[dap_ap_get_select(tap->dap)].memaccess_tck = 80;
        armv7a->arm.dap = tap->dap;
 
        cortex_a->fast_reg_read = 0;
@@ -3321,6 +3355,32 @@ COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command)
        return ERROR_OK;
 }
 
+COMMAND_HANDLER(handle_cortex_a_dacrfixup_command)
+{
+       struct target *target = get_current_target(CMD_CTX);
+       struct cortex_a_common *cortex_a = target_to_cortex_a(target);
+
+       static const Jim_Nvp nvp_dacrfixup_modes[] = {
+               { .name = "off", .value = CORTEX_A_DACRFIXUP_OFF },
+               { .name = "on", .value = CORTEX_A_DACRFIXUP_ON },
+               { .name = NULL, .value = -1 },
+       };
+       const Jim_Nvp *n;
+
+       if (CMD_ARGC > 0) {
+               n = Jim_Nvp_name2value_simple(nvp_dacrfixup_modes, CMD_ARGV[0]);
+               if (n->name == NULL)
+                       return ERROR_COMMAND_SYNTAX_ERROR;
+               cortex_a->dacrfixup_mode = n->value;
+
+       }
+
+       n = Jim_Nvp_value2name_simple(nvp_dacrfixup_modes, cortex_a->dacrfixup_mode);
+       command_print(CMD_CTX, "cortex_a domain access control fixup %s", n->name);
+
+       return ERROR_OK;
+}
+
 static const struct command_registration cortex_a_exec_command_handlers[] = {
        {
                .name = "cache_info",
@@ -3362,7 +3422,14 @@ static const struct command_registration cortex_a_exec_command_handlers[] = {
                .help = "mask cortex_a interrupts",
                .usage = "['on'|'off']",
        },
-
+       {
+               .name = "dacrfixup",
+               .handler = handle_cortex_a_dacrfixup_command,
+               .mode = COMMAND_EXEC,
+               .help = "set domain access control (DACR) to all-manager "
+                       "on memory access",
+               .usage = "['on'|'off']",
+       },
 
        COMMAND_REGISTRATION_DONE
 };
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